TL16C752B-EP: About RX time-out

Gk 110

Expert 2440 points

Part Number: TL16C752B-EP

Hi, to whom it may concern

I ask about TL16C752B.

We have two question, could you please answer?

Q1 ;

　When the RX time-out is happened, what is the LSR[0] register value?

Is it “1” or “0”?

Q2 ;

When the RX time-out is happened, Interrupt source is “stable data in RX FIFO” was written at Table 4 in the datasheet.

How status is this?

In this case, I'd like to know how to control and how to solve by software.

Could you please give us any advices?

Best regards,

Gk110

over 5 years ago

0 Wade Vonbergen over 5 years ago

TI__Guru 62930 points

GK,
I will need to research Q1, to determine if Bit 0 is set. I will get back to you.

For Q2, I am not sure what you mean. BTW, you indicate "stable" This should be "stale" Ie, old or partial data.
To clear the interrupt, read the RHR. I suspect the answer to Q1, is that bit 0 is set in this condition. I will confirm.

Regards,
Wade

0 Wade Vonbergen over 5 years ago in reply to Wade Vonbergen

TI__Guru 62930 points

GK,
I wanted to update you on my assessment.
The RX timeout interrupt is triggered after no additional data is received (with at least one word in FIFO) on the TL16C752B after 4X wordlength + 12 bits.
The RX timeout is indicating that there is data in the RX FIFO, but no additional data is arriving. The normal FIFO threshold to trigger host to grab data did not get hit. Thus this interrupt can be treated similar to the RX FIFO threshold. The host can grab remaining FIFO data.
Reading data will clear the interrupt.
LSR[0] should be set, as this condition indicates data is in FIFO.

If this answers your question, please click "Verify it as the answer"
Regards,
Wade

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TL16C752B-EP: About RX time-out