DP83867CR: Feedback on schematic implementation of PHY

Hey Rob,

Thank you very much for the redlines your advice was critically important and helped a lot!

I have a question about one of them.

1. Does section 6.1 only apply to the PHY?

2. Can I leave P10 floating?  It sounds like leaving it floating was the intention of your comment.

I think the RJ45 connector I planned on using won't work.  I've attached the schematics (22.jpg) and it shows the center tap pins connected together.  

Should I switch to a connector with magnetics oriented like the connector in 21.jpg?

If this shows up in the post as pictures - the first pic is the connector I'm wondering if I should switch to, the second picture is the one I currently have in my design.

Hi Robbie,

I agree that your original magnetic selection is not ideal for the DP83867 because the center taps are all shorted together.

The image you posted of your second magnetics selection (top image) has a good schematic for the DP83867.

Best Regards,

Oh great!

Does that mean the TRCT1-4 pins should be connected to ground via caps as shown in the data sheet like you originally pointed out?  I only ask because the magnetics look so different I want to make sure there isn't another detail I'm missing.

That's correct. TRCT1 - TRCT4 from the magnetics you found should have individual 0.1uF caps to bypass any noise to ground.

Best Regards,

Rob,

Thank you for the comments.  I've attached an updated schematic that I think fixes the problems I had.  Do I need to break out the JTAG pins for the DP83867?  I feel like there is no point because I can't use them anyways since I can't reprogram this chip.

Thanks!

Bel_RJ45_Schematics.pdf

Rob,

1. Do I need to break out the JTAG pins from the PHY for any reason? It seems like even if I did I couldn't do anything with them.
2. Should the traces from the TD_P_A, TD_M_A, etc... (connection between the PHY and the connector/magnetics) be impedance controlled?
2a. Should they be length matched?
2b. I'm assuming that should be as short as possible as well?

Hi Robbie,

1. You do not need to break out the JTAG port if it will be unused.

2. Yes, those are recommended to be impedance controlled for superior MDI performance from EMI EMC perspective. Since you are doing a "standard gigabit application" you can probably be OK with just estimating the impedance with a layout tool.

2a. They should be length matched within 100 - 200mil. This is really loose as there is a symbol alignment on these traces anyways.

2b. Yes, keep the MDI to a minimal length if possible, but applications where the MDI traces are up to 6 inches are common and not a large issue.

Best Regards,

Rob,

Thank you for the response! 

Per your comment:

"2. Yes, those are recommended to be impedance controlled for superior MDI performance from EMI EMC perspective. Since you are doing a "standard gigabit application" you can probably be OK with just estimating the impedance with a layout tool."

Do you mean estimate it to a 100ohm differential impedance and massage the PCB stackup and diff. trace geometry to achieve that?  For example with LVDS you terminate with 100R diff. and set the trace impedance to 100R differential.  In this application I'm driving inductors so what should my target impedance be for the 4 diff. pairs?

Robbie,

Yes, estimate the 100R diff and choose your trace width, spacing, and stackup height to achieve the impedance.

You should target 100R differential, 50 ohm Z0 for the MDI.

Best,

By MDI interface you mean MDIO/MDC?

1. If MDIO/MDC are 50ohm lines do they need a 50ohm termination at the FPGA?

2. What about the interface to the MAC?  Should they be 50ohm transmission lines with a 50 termination resistor at the FPGA side as well?

Screenshot of MAC interface side attached.