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ISO5500: Generating spurious fault signals

archit khandelwal
Prodigy 190 points

Part Number: ISO5500

Hello everyone. I am developing a 3kw solar inverter circuit. Currently, I am using ISO5500 to drive IGBT and I have also developed a DC/DC isolated supply using UC3845 with output +15/-8v and .5A for the gate drive supply . The problem is that whenever I connect this dc/dc supply and run my circuit ISO5500 starts producing faults and my system shuts down and when I replace this supply with 15V step-down transformer then I face no such issue the ISO5500 works fine without generating any fault signal.  I need help in identifying why ISO5500 is generating a fault signal. Do I need to take any protective measure regarding spurious faults or if the problem is in the Isolated power supply then how to design it correctly for the gate drive application.

Best regards and thanks in advance.

  • 0
    TI__Intellectual 1665 points
    Hi Archit,

    Could you please share with us the schematic of the gate driver and power supply circuits? Also, could you please share some scope captures of the PWM signal, fault signal, DESAT pin voltage, and power supplies of VEE-P, VEE-L, and VE? With that, we can help you out better.

    With Regards,
    Xiong
  • 0 in reply to Xiong Li
    Prodigy 190 points

    Hi Xiong,

    I have attached the schematics of the gate driver and the power supply.

    I have followed the recommended circuit in case of the power supply as provided in the datasheet. The Ic I have used is UC3843.

    In the Driver circuit, I have used a zener(Z1) and resistor(R2) combination to generate a -ve voltage of - 8v. Other than that I followed the recommended circuit

    As I only have 1 two channel oscilloscope, I am unable to provide you with the scope captures of so many signals altogether.

    I have some doubts-

    1. Can fault signal be only generated if Desat pin detects a voltage rise above a certain level? .Can some noise on the input side affect the fault signal sensing via the microcontroller? What can be the other possible reasons if the microcontroller is detecting a Low State on the fault pin?.

    2. Can UC3843 based Switching power supply act as a source for the gate driver input if designed properly?. If not then what can be the other options that i can look into for the driver supply.   I am taking the input for the UC3843 based power supply from solar panel string, voltage is ranging from 150-350V.

    Regards 

    Archit

  • 0 in reply to archit khandelwal
    TI__Intellectual 1665 points

    Hi Archit,

    Thanks for the information. The schematic looks fine to me. 

    1. As designed, the /FAULT signal should go low when the voltage on DESAT pin goes above the threshold value. However, external noises may also corrupt the signal on the /FAULT pin. Have you added a 3.3k pull up resistor on the /FAULT pin as recommended. Also, what is the output state when the /FAULT goes to low? In order for us to better understand the situation, please measure the power supply voltages, DESAT pin voltage, and PWM input signal. 

    2. UC3843 based design is able to provide the right power supplies to ISO5500 if designed properly. 

    With Regards,

    Xiong

  • 0 in reply to Xiong Li
    Prodigy 190 points
    Hi Xiong,
    The "R3" resistance in the schematics is what we have for the 3.3k pull-up resistor, connected between the VCC1 and the FAULT pin.

    In our code we have a ISR of around 150us which senses the state of the /FAULT pin and if it goes low we disable the pwm and trip our inverter circuit. In our experiments we observed the state of the /FAULT signal sensed via a GPIO pin, we noticed that the whenever a /FAULT low occurs the /FAULT output is not latching to zero state even without providing /RESET signal . Then we added a counter variable just to count the no. of LOW we obsereved that the counter value is increasing in a randomn fashion say 10-15 times/sec and the circuit working properly if we comment the disabling of PWM part in code. We also observed a significant increase in the change in count value(upto 25-30 units /s) when we increased the DC link voltage accross inverter.

    In the datasheet it's written that /Fault output remains to LOW state until cleared by /RESET pulse. So if the /FAULT is getting low due to DESAT then why it's not latching and if it's due to the input side noise then what else we can add other than 3.3k ohm pull up resistor.

    Regards
    Archit
  • 0 in reply to archit khandelwal
    TI__Intellectual 1665 points
    Hi Archit,

    Based on your description, it seems some noises are coupled to /FAULT pin and caused the false protection. The /FAULT pin would latch to low only when a DESAT protection is triggered which is not the case in your application.

    To proceed, I would recommend:

    1. Measure the voltage on the /FAULT pin and voltage on the DESAT pin.
    2. Reduce the pull-up resistor to 1k and add a filtering capacitor between /FAULT pin and GND. The time constant can be determined based on the duration of /FAULT being low.
    3. It is clear to me that the SMPS has injected some noises to the gate driver circuits. You may want to improve the design of the SMPS before using it to power the gate driver circuits.

    With Regards,
    Xiong