Transmitting a 20MHz clock between 2 boards using a pair of SN65LVDS179 transceivers. In operation, the clock bursts in sequences of 14 cycles, then goes idle for a period of time, then repeats 14 cycles, etc. On transmit end, the clock signal being transmitted, when measured at the corresponding input pin on the LVDS transmitter is cycling with the expected 0101... sequence (0V to ~3.2V), settling at 0V when idle. At the output of the LVDS receiver on the receive end, the clock that is output is at 3.2V when idle, and when cycling the burst of 14 pulses, the pulses are inverted, so that each cycle goes to 0 from the inverted idle state (so, 3.2V to 0, back to 3.2V, etc).
Probing with a DSO, the VIA and VIB (diffential pair) signals at the differential inputs at the receive chip (specifically, yellow probe is on the non-inverting side of the 100 ohm term resistor, blue trace is on the inverting side of the term R, scope ground leads tied to signal ground - reference Figure 15 in the data sheet), I see the waveforms in the following figure (red trace is Ch1-Ch2):
I was expecting to see the blue and yellow traces to move in opposition, that is, when yellow goes hi, blue goes low (relative to the common-mode offset), similar to waveforms for VIA/VIB shown in Figure 15 of the data sheet.
The red trace shows when idle there is a DC offset (it is non-zero, just like the output from the receiver chip).
I repeated the measurement, at the output of the transmitting chip, by placing a 100ohm R across the VIA/VIB pins and measuring each side of R with the two probes. Got the same result.
Replaced the transmit chip with another one and repeated. No change.
Can anyone tell me if I'm measuring/interpreting this incorrectly, and why the output at the receive end is inverted from what is being input at the transmit end?
Thank you.
