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DS90UB925Q-Q1: The DS90UB925QSQ implementation outputs image data to the display in a relatively short amount of time

求知元
Prodigy 20 points
Part Number: DS90UB925Q-Q1

The main problem at present is that DS90UB925QSQ needs to wait around 5s after receiving imx6 image data to serialize the image data normally (it can be displayed).

Here are the tests and results:

1. Under the condition that the image is normally displayed (it has been waiting for 5s), the PDB pin of 925 is pulled down to enter the power down mode. There is no video output during the period.

2. Under the condition that the image is normally displayed (it has been waiting for 5s), write register 0x01 of 925 and reset it. It is found that it still needs about 5s to restore the normal image output

Help confirm: does it take so long for DS90UB925QSQ to reset each time to send the image data?

  • 0
    TI__Genius 10475 points
    Hello,
    What deserializer are you using the 925 with and what is the PCLK frequency? For lock time, please refer to tPLD spec in the datasheet. It is a function of the PCLK frequency.
    Please ensure the VDD supplies have reached their required operating levels before issuing PDB = high to reset the device. Also the incoming signal needs to be present and stable at the deserializer input when that device is pwoered up, otherwise PDB needs to be issued (or digital reset) to the deserializer so the system can operate properly.
  • 0
    TI__Mastermind 30515 points
    Hi,
    UB925 can work directly after ~10ms of RESET/PDB. in your case, pls check your system level setting, it could other factor results into this issue.
    to confirm it from UB925 side, you can measure the UB925's output, and compare it with UB925's PCLK input. the relation should be 35 times.
    if yes, pls check the paired part output, does it have any output within 5s? if yes, it could be other module issues.

    best regards,
    Steven
  • 0 in reply to Steven(Shenzhen) Shi
    Prodigy 30 points

    Thank you for your reply,I wiil check it.

  • 0 in reply to Palaniappan Manickam
    Prodigy 30 points
    We use 926q-q1 as deserializer and both 925 and 926's registers are using default setting. PLL is locked(refer to 926's LOCK pin) soon after we powered up the board,but the screen is still blank.I am sure VDD supplies have reached their operating levels and output signal from i.mx6 is stable too.I.mx6's PCLK frequency is 14.25MHz and out default LFMODE setting is L(frequency range 15-85MHz) but the PLL can't lock when we change our LFMODE is H(frequency range = 5- 15MHz).
  • 0 in reply to user5847747
    TI__Mastermind 30515 points
    1. can you improve the PCLK freq. for debug the link whether it is ok?
    2. pls measure the PCLK output in UB926's PCLK pin and the PCLK input in UB925's PCLK pin, and compare it based on your mode setting.

    regards,
    Steven
  • 0 in reply to Steven(Shenzhen) Shi
    Prodigy 30 points

    sorry for late reply. We find deserializer's data pin can output data soon after serializer start transmission.It not a 925 or 926 issue.Thank you for help!