DS80PCI102: Configuring for PCIe, SGMII and SRIO

joe lindula

Part Number: DS80PCI102
Other Parts Discussed in Thread: 66AK2H14

Hello, I'm using the 66AK2h14 ARM+DSP on my new design and I have decided to use the DS80PCI102 Repeater on the PCIe, SRIO and SGMII lanes. The max lanes distance going over FR4 is about 16 - 25 inches and using 4-mil traces. The rates for the links are SGMII 1.25Gbps, SRIO 3.125Gbps and PCIe 2.5Gbps. The ARM+DSP PCB will be a 6U VPX card that plugs into a VPX 4-SLOT backplane. I going to place the repeater as close as possible to the DSP processor and will do the same on the other VPX board which as a Xilinx FPGA.

I've set the DS80PCI102 the same for each protocol:

Table 2:
Level 7 (FR4 20-inch 4-mil trace)
EQA1/EQB = 1K pull-up
EQA0/EQB0 = Float

Table 3.
Level 12
VOD_SEL = Float
DEMA/DEMAb = 1K pull-up

RXDET floating for Auto-RX Detect

Does this seem like a good configuration for all the protocols?

Thanks,
Joe

over 5 years ago

0 Lee Sledjeski over 5 years ago

TI__Mastermind 43795 points

Hi Joe,

I think the settings are okay to get started. I would recommend to leave a few inches between the processor and the DS80PCI102. Even the lowest CTLE setting has some gain. The space between the two chips will allow enough attenuation to compensate for the PCI102 lowest gain setting.

Regards,

Lee

0 joe lindula over 5 years ago in reply to Lee Sledjeski

Mastermind 6850 points

Lee,

HI, thanks for responding to my post. Say, I need to operate in a temp range of -45C - 100C. Is there a device that can operate in this temp range?

Thanks,
Joe

0 Lee Sledjeski over 5 years ago in reply to joe lindula

TI__Mastermind 43795 points

Hi Joe,

We do not have a device like this specified to operate at 100C. The DS80PCI102 has just enough thermal headroom to work at 100C, but it is not specified that way in the datasheet. Here is a quick calculation based on keeping the junction temperature at 105C or lower. Junction temperature beyond 105C will work to decrease the long term reliability of the device.

Package Theta JA = 35 degrees C / Watt

Worst case power = 2.5V x 63mA = 157.5 mW

35 C/W x 0.1575 mW = 5.5 degrees C

Junction temperature @ 100C ambient = 105.5C

Regards,

Lee

0 joe lindula over 5 years ago in reply to Lee Sledjeski

Mastermind 6850 points

Lee,

HI, can you please look over my calculations:

PCIE:

SGMII Calculations:

SRIO Calculations:

My numbers look good for SGMI 0.977V after the Receiver, but I'm the PCIe is 1.67V and the SRIO is 1.99V.

I must be doing something wrong in my math or I'm not understanding the datasheet correctly.

Can you help clear things up for me please.

Thanks,

Joe

0 Lee Sledjeski over 5 years ago in reply to joe lindula

TI__Mastermind 43795 points

Hi Joe,

I would not use more than 6 dB of DEM. You should not need it with these lower datarates.

The equalizer will not boost the lower frequencies as much as the higher frequencies. It is impossible for the parts to deliver output voltages in excess of ~ 1.3V

Regards,

Lee

0 joe lindula over 5 years ago in reply to Lee Sledjeski

Mastermind 6850 points

Lee,

Hi, so are you saying to say with Level 12 for DEM and Level 7 for the Equalizer?

Last, my math must be wrong on the Vr, what is the best way to calculate Vr, the voltage after the receiver?

Thanks,
Joe

0 Lee Sledjeski over 5 years ago in reply to joe lindula

TI__Mastermind 43795 points

Hi Joe,

You really won't be able to calculate the voltage level after the receiver with that type of equation.

For a starting point with this application I would recommend using

DEM = Level 11 (1.0V with -3.5dB DEM)

EQ = Level 2 (+3.4 dB @ 1.25 GHz)

It it much easier to start with low equalization values and increase the setting if any tuning needs to be done.

Here is a link to linear equalization which can help give some background.

www.ti.com/.../slyt629.pdf

Regards,

Lee

0 joe lindula over 5 years ago in reply to Lee Sledjeski

Mastermind 6850 points

Lee,

HI, are you recommending DEM/EQ = 11/2 for sgmii, pcie, and srio channels?

Joe

0 Lee Sledjeski over 5 years ago in reply to joe lindula

TI__Mastermind 43795 points

Yes

0 joe lindula over 5 years ago in reply to Lee Sledjeski

Mastermind 6850 points

Lee,

HI, here are my new numbers:

If my math is not right can you help me clear things up.

Thanks,

Joe

0 Lee Sledjeski over 5 years ago in reply to joe lindula

TI__Mastermind 43795 points

Joe,

Equalizers will not amplify the lower frequency content of the original signal.

I have attached a plot in the frequency domain - notice the combination of trace attenuation + equalizer gain results in a flat total response.

The time domain waveform shows how this would look in an eye diagram.

Regards,

Lee

0 joe lindula over 5 years ago in reply to Lee Sledjeski

Mastermind 6850 points

Lee,

Hi, I do not declare to be an expert on the topic so please forgive me for not seeing the obvious. Can you comment on my math calculations. I'm concerned about the value of Vr which would be the voltage of the received signal that goes onto the processor. Are you saying that Vr can never go above 1Vpp?

Respectfully,
Joe

0 Lee Sledjeski over 5 years ago in reply to joe lindula

TI__Mastermind 43795 points

Hi Joe,

No problem. Yes the Vr signal at the processor will not go above 1Vpp. The maximum output voltage of the DS80PCI102 is set by the DEM table in the datasheet. I would not recommend to use Level 12, -9 dB of DEM will not give good results. I would recommend using Level 11 instead, a 1.0V VOD with -3.5dB of DE is the normal output waveform for PCIe Gen1.

Regards,
Lee

0 joe lindula over 5 years ago in reply to Lee Sledjeski

Mastermind 6850 points

Lee,

HI, so in my calculation of Vr I get 2.1543V, but the DEM setting of Level 11 will limit the voltage to VOD (Vp-p) of 1.0? Is that the correct understanding?

0 joe lindula over 5 years ago in reply to joe lindula

Mastermind 6850 points

Lee,

Does my math look correct?

0 joe lindula over 5 years ago in reply to joe lindula

Mastermind 6850 points

Lee,

The Equalizer Setting on Table 2 is that the same an Pre-emphasis, where the signal is boosted to go over a long backplane trace?

0 Lee Sledjeski over 5 years ago in reply to joe lindula

TI__Mastermind 43795 points

Hi Joe,

Your math is assuming a constant gain across frequency. The Vt portion of the waveform is actually comprised of low frequency sine wave components. These low frequencies are not boosted by the equalizer. You can think of a equalizer as boosting the signal transitions but not boosting the steady state amplitude.

Regards,

Lee

0 Lee Sledjeski over 5 years ago in reply to joe lindula

TI__Mastermind 43795 points

Hi Joe,

It is not really the same as pre-emphasis. Consider the following examples of signals at the input and output pins of the DS80PCI102.

Note "equalizer output" is an internal signal going to the driver input. The driver output amplitude is set by the VOD setting, not the input signal amplitude.

Input -> equalizer -> driver -> Output

EQ Gain = 3 dB @ 1.25 GHz, VOD setting = 1V

Vin = 100mVpp sine wave at 1.25GHz

Vequalizer output = Vdriver input = ~ 140mVpp sine wave @ 1.25GHz

Vout = 1000mVpp square wave @ 1.25 GHz

EQ Gain = 6 dB @ 1.25 GHz, VOD setting = 1V

Vin = 100mVpp sine wave at 1.25GHz

Vequalizer output = Vdriver input = ~ 200mVpp sine wave @ 1.25GHz

Vout = 1000mVpp square wave @ 1.25 GHz

EQ Gain = 6 dB @ 1.25 GHz, VOD setting = 1V

Vin = 1000mVpp sine wave at 1.25GHz

Vequalizer output = Vdriver input = ~ 1400mVpp sine wave @ 1.25GHz (approximate maximum dynamic range of internal circuits)

Vout = 1000mVpp square wave @ 1.25 GHz

Regards,

Lee

0 joe lindula over 5 years ago in reply to Lee Sledjeski

Mastermind 6850 points

Lee,

Is there a recommendation which OUT port should be connected to the processor? I'm just thinking about your statement, " Yes the Vr signal at the processor will not go above 1Vpp".

Thanks,
Joe

0 Lee Sledjeski over 5 years ago in reply to joe lindula

TI__Mastermind 43795 points

The OUT ports are identical.

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DS80PCI102: Configuring for PCIe, SGMII and SRIO