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TLK10232: Working with TLK10232 at 1,25 Gbps in transparent mode

José R. Quintanillla
Prodigy 120 points
Part Number: TLK10232

Working with TLK10232 at 1,25 Gbps in transparent mode

Is it possible working with this device at 1,25 Gbps with the 8b/10B decoder/encoder and channel Sync Block disabled?. In this mode, the traffic between low speed serdes and high speed serdes would pass with no analisys (transparent), working like a 1,25Gbps CDR device.

best regards,

  • 0
    TI__Guru 64326 points

    Hello,

    HS_DEC_BYPASS and HS_ENC_BYPASS bit fields can be used to disable the 8b/10b encoding on the HS side of TLK10232. There is still a 8b/10b decoder on the low speed side and Sync blocks that cannot be turned off. Could you explain your application? TI does have devices capable of CDR at >1.25 Gbps that may work for your application. 

  • 0 in reply to Malik Barton57
    Prodigy 120 points

    Hello,

    It is a equipment with two SFP conected to a FPGA. It have to work at Ethernet 1G and 10G. The interface of the FPGA can work like  a XAUI (for ethernet 10Gbase-R) or a SFI line at 1,25 Gbps. There is not any problem in XAUI mode for 10GBase-R

    When it is working at 1G Ethernet, there could be two types of SFP:

    - Optical SFP for 1000baseX with 8B10B (no problem).

    - Electrical SFP with SGMII interface. The SGMII interface can work at 1,25 Gbps 8B10B, or adapting a 10BaseT/100BaseT Ethernet. When operating at 10 or 100Mbps, the SGMII interface interface “elongates” the frame by replicating each frame bit 10 times for 100 Mbps and 100 times for 10 Mbps. So, there is not 8B10B code.

    In the Figure 5-1 of the data sheet (Block Diagram Showing General Purpose SerDes Mode), there a bypass for both 8b10b coder/decoder. Is it possble to use this bypass with the FIFOs disabled?

    best regards,

  • 0 in reply to Malik Barton57
    Prodigy 120 points

    Hello, second reply with a correction

    It is a equipment with two SFP conected to a FPGA. It have to work at Ethernet 1G and 10G. The interface of the FPGA can work like  a XAUI (for ethernet 10Gbase-R) or a SFI line at 1,25 Gbps. There is not any problem in XAUI mode for 10GBase-R

    When it is working at 1G Ethernet, there could be two types of SFP:

    - Optical SFP for 1000baseX with 8B10B (no problem).

    - Electrical SFP with SGMII interface. The SGMII interface can work at 1,25 Gbps 8B10B, or adapting a 10BaseT/100BaseT Ethernet. When operating at 10 or 100Mbps, the SGMII interface interface “elongates” the frame by replicating each frame byte 10 times for 100 Mbps and 100 times for 10 Mbps. So, there may not be fully compliant with 8b/10b 1000bse code.

    In the Figure 5-1 of the data sheet (Block Diagram Showing General Purpose SerDes Mode), there a bypass for both 8b10b coder/decoder. Is it possble to use this bypass with the FIFOs disabled?

    best regards,