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DS125DF111: DS125DF111: EQUALIZER SETTING question

Part Number: DS125DF111
Other Parts Discussed in Thread: SIGCONARCHITECT
Hello.
We are evaluating the characteristics of the DS125DF111.
The operation setting uses SIGCONARCHITECT.
So please tell me about the following.
1. How to set the equalizer(CTLE and DFE)?
2. Where can I check the equalizer setting at that time by reading the register value?
Best regards,
  • Greetings,

    1). Please use SigconArchitect GUI. To set CTLE and DFE, please go to SigconArchitect "High Level Page" tab. Then you can select "RX EQ/DFE" tab. This specifies different adapt modes.

    2). Using SigconArchitect GUI, please got to "High Level Page" tab and then "Device Status" tab.

    To know the exact register settings, there are two ways we can do this:

    1- Please note data sheet section 7.5.1.12. To read equalizer settings, you can read reg 0x52. Also, this section specifies how to manually set equalizer settings as well.

    2- Please go to SigconArchitect "Low Level Page". In this tab you can read register values.

    You can make changes in the GUI and then compare low level register settings to know the exact changes made by SigconArchitect.

    Regards,,nasser

  • Thank you for the information.

    Is it possible to confirm  the setting of DFE (Tap 1 ~ 5) by reading the value of reg "0x71 ~ 0x75"?

    Best regards,

  • Greetings,
    Yes you can read DFE weight by reading regs 0x71 through 0x75. In majority of applications, I believe tap 1 seems to have the highest influence. Suggestion is to use SigconArchitect and fine tune DFE settings. Then go to the low level page to get the exact register settings.
    Regards,,nasser
  • Thank you for your information.

    When adaptive mode was 2, it was confirmed that the value of 0x52 of "Low Level Page" was changing automatically.
    After that, on the "High Level Page" tab, the adaptive mode was set to 0, and the CTLE setting was changed. However, when 0x52 of "Low Level Page" was confirmed, it was the same value as before CTLE change.
    Is this correct?

    Best regards,

  • Hi

    You will also need to override the register bit at 0x2D[3].  This bit must be set to [1] in order to override the current CTLE value with a new value in register 0x03[7:0].

    Regards,

    Lee