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SN65LBC182: Issue with Indeterminate State on Output R

Fabio Soriano
Intellectual 2655 points
Part Number: SN65LBC182
Other Parts Discussed in Thread: THVD1500

Hi Team,

I received the following request:

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We have problems with RS485 communication. We use TI SN65LBC182D component. When the line is idle (master and slaves are on bus and in receive mode), RO (receive output) is not logic 1 always.

Above indeterminate condition (marked with ?) causes RO to random case. TI defines this condition as fail-safe condition. Below schematic is our master device. When the bus is in idle, Vid is always near to 0 V. This is indeterminate state. We need logic 1 of RO output when bus is idle. Because the microcontroller cannot detect this error data frame.

 

 

Can you suggest me something or any TI component to solve this problem?

I am waiting your comments.

################################

Regards,

Fabio

  • 0
    TI__Guru 62910 points
    Hi Fabio,

    Your understanding of the problem is correct. There are a couple of different solutions.

    One would be to use a transceiver with a "failsafe" function implemented in its receiver. This means that a differential input of 0 V would correspond to a high-level (rather than indeterminate) output. An example of such a device would be THVD1500, which is pin-to-pin compatible with SN65LBC182D.

    Another solution would be to implement failsafe biasing externally and ensure that the differential input voltage seen by the transceiver is >200 mV when the bus is idle. This could be done by decreasing the values of R21 and R23 in the above schematic.

    For more information on RS-485 failsafe and how to compute resistance values for an external bias network, you can reference this blog:

    e2e.ti.com/.../rs-485-basics-two-ways-to-fail-safe-bias-your-network

    Please let me know if you have any questions.

    Best regards,
    Max