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Hi , initially setup M/N ratio for FC =4000 of 6/250 with HS_CLK_DIV = 1 , but the jitter is too much.
The sensor requires 48MHz and these values give that output but I think now that HS_CLK_DIV should be 4 or more to satisfy equation 2 on page 25 of 953 datasheet
could you recommend the best values closest to 48MHz to give the least jitter.
Patgen is fine , I am able to setup YUV422 8 bit in the 953 and stream out through the 954 in to the csi to usb3 device and display a color bar on PC
Also , we are running the BC at 25Mbps between 953 and 954 over STP , could this affect the clock?
Apologies , typo in M value , it was 3 with the div ratio of 4 , getting Fc = (4000) x 3 / (4 x 60) .
I am going to check that the clkout resistors satisfy the >35K load requirement , in case this is the issue.
for the 953 board we have Rlow = 40.2K and Rhigh = 10M
For the 954 we have Rhigh =78.7K and Rlow =97.9K giving a vstrap voltage of 0.995
looking at the ALP screenshot , whether we are at 50MHz clock or 48MHz clock I get the 3840 bytes x 1080 lines at the RX port.
this is YUV422 8bit
I take it that the 0x72 register of 954 should be set to 0x1e for this stream type. It is then passed on out to the CX3 device without any changes
Is there anything to do on the port forward side other than
1: set clk to 400MHz , enable port forward 0x20,0x20 , continuous clock on ?
we had tried the faster rate but lost i2c comms , ALP shows the link up at 50Mbps but we cannot program the sensor.
Will try programming at low speed then setting link to 50Mbps after setup .