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Linux/DS90UB960-Q1: DS90UB960---DS90UB953 Multi Camera Line-Concatenated

CHOI KILSOO
Prodigy 180 points
Part Number: DS90UB960-Q1
Other Parts Discussed in Thread: DS90UB964-Q1, , DS90UB953-Q1

Tool/software: Linux

HI Sir

We are

DS90UB960---DS90UB953 

and

Use four cameras.

'1920x1080 YUV422 8bit MIPI 2Lane'

Each camera output has been confirmed.

What we want to do is

RX0, RX1 => CSI 0 port.

RX2, RX3 => CSI 1 port

As above, two cameras are output to one Csi Port
It is output at 3840(1920*2) x 1080 resolution.

I have set the DS90UB960 for this, but it does not work.
This is the register we set.

once 2 camera(rx0,rx1 to csi port0)

0  1   2   3  4   5   6   7  8  9  a   b   c  d  e  f    0123456789abcdef

00: 60 00 1e 30 c2 01 00 e2 1c 10 80 79 0f 09 00 ff    `.?0??.????y??..

10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 07    ..............??

20: c0 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ?<..............

30: 00 00 01 21 00 00 00 03 00 00 00 00 00 00 00 00    ..?!...?........

40: 00 a3 01 01 00 00 00 00 00 00 00 00 12 53 fd 64    .???........?S?d

50: 00 00 00 03 00 00 00 00 5e 00 00 30 1a 50 00 00    ...?....^..0?P..

60: 00 00 00 00 00 52 00 00 00 00 00 00 00 78 88 88    .....R.......x??

70: 6b 6c e4 04 38 0f 00 c5 00 01 0f ff 20 00 00 00    kl??8?.?.??. ...

80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

b0: 02 69 00 08 25 00 18 00 88 03 03 74 80 00 00 00    ?i.?%.?.???t?...

c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

d0: 00 43 84 0f 60 f8 03 00 00 00 00 08 00 00 00 00    .C??`??....?....

e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

f0: 5f 55 42 39 36 34 00 00 00 00 00 00 00 00 00 00    _UB964..........


Thank you for your guide.

  • 0
    TI__Expert 3390 points
    Hi Choi,

    Are you using a DS90UB964-Q1? The register dump is from a 964 device.

    Also, what is not working? It appears you are getting video but is it just not concatenated?

    Also how much video data are you trying to output? Like to total line rate per csi lane?

    Additionally, why is Register 0x1F=0x07, which would have the Des set to output 400Mbps. Is this intentional? From your configuration, I think you are outputting more than 400Mbps/lane.

    Regards,
    Mandeep Singh
  • 0 in reply to Mandeep S
    Prodigy 180 points
    Thank you for quick response.

    Are you using a DS90UB964-Q1? The register dump is from a 964 device.
    >
    I doubt it either. The module(H/W) is printed on the DS90UB960-Q1.

    Also, what is not working? It appears you are getting video but is it just not concatenated?
    >
    It does not operate (output) when two rx is set to one csi port.

    Also how much video data are you trying to output? Like to total line rate per csi lane?
    >
    I want 4 lanes to be output(3840x1080) on one CSI port.

    Additionally, why is Register 0x1F=0x07, which would have the Des set to output 400Mbps. Is this intentional? From your configuration, I think you are outputting more than 400Mbps/lane.
    >
    It is not intentional.
    If it is set higher than 400Mbps, the image will be output and then stopped.

    Regards,
    Choi
  • 0 in reply to CHOI KILSOO
    TI__Expert 3390 points
    Hi Choi,

    Are you trying to output from the 960 CSI port in 2 lane or 4 lane?
    You have the SER recieving 2 lanes and that is okay but you are outputting 2 lanes currently on the DES and with what I calculated below for the total video throughput (~1.244G/lane for 4 lanes = 4.976Gbps), there's not enough bandwidth on the CSI port to output all the data in 2 lanes. The max CSI output on the 960 in 4 lanes is 6.4G/lane. In 2 lanes, the max you could output is 3.2G/lane. With the amount of data you are trying to ouptut, it should be 4 lane. If that's correct, can you set register 0x33[5:4] = 00 on the DS90UB960-Q1.

    If that doesn't help, Please see my responses below.

    Are you using a DS90UB964-Q1? The register dump is from a 964 device.
    >
    I doubt it either. The module(H/W) is printed on the DS90UB960-Q1.
    -- From the register dump, it is confirmed that the device is DS90UB964-Q1. Registers 0xF1-0xF5 are showing a value of U B 9 6 4. Please re-check this and update the device if necessary as the 964 is not compatible with the 953.

    Also, what is not working? It appears you are getting video but is it just not concatenated?
    >
    It does not operate (output) when two rx is set to one csi port.
    -- Okay, so one output is okay but two are not? is that correct?
    -- Also, have you tried round robin or another type of forwarding? What were the results?

    Also how much video data are you trying to output? Like to total line rate per csi lane?
    >
    I want 4 lanes to be output(3840x1080) on one CSI port.
    -- So, I suspect the bits per pixel are 16, since it's YUV422 8-bit and I'm assuming the fps is 60? That would give us a line rate of about 1.244G/lane with some overhead for a 4 lane configuration.

    Additionally, why is Register 0x1F=0x07, which would have the Des set to output 400Mbps. Is this intentional? From your configuration, I think you are outputting more than 400Mbps/lane.
    >
    It is not intentional.
    If it is set higher than 400Mbps, the image will be output and then stopped.
    -- Can you set 0x1F = 0x00, so the CSI output is 1.6G/lane. You are outputting more than 400M/lane.

    Additionally, Can you set 0x20 = 0xCC. This will map Rx Port 2 and 3 to CSI port 1, even though it's disabled, it's best practice to have it set this way.
  • 0 in reply to Mandeep S
    Prodigy 180 points

    As you said 0x20 = 0xCC, I could set the clock high (0x1f = 0x01) Even if Disabled, I need to set the port. Thanks.
    But if you set 0x1f = 0x00, it stops working.
    We will change to 26mhz crystal and check it out.

    But I increased the clock and made Des a 4lane
    rx0, rx1 to csi port0 can not be output simultaneously.

      For Line-Concatenated
    Does register 0x70 ~ 0x7f need to be set?

    This is a new register dump.

    0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
    00: 60 00 1e 40 d0 01 00 fe 1c 10 7a 7a 0f 09 00 ff `.?@??.???zz??..
    10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 ..............?.
    20: cc 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ?<..............
    30: 00 00 01 01 00 00 00 03 00 00 00 00 00 00 00 00 ..??...?........
    40: 00 a9 71 01 00 00 20 00 00 00 00 12 12 53 5d 64 .?q?.. ....??S]d
    50: 00 00 00 04 06 00 00 00 5e 00 00 30 1a 50 00 00 ...??...^..0?P..
    60: 00 00 00 00 00 52 00 00 00 00 00 00 00 78 88 88 .....R.......x??
    70: 1f 6c e4 04 38 0f 00 c5 00 01 02 01 20 00 00 00 ?l??8?.?.??? ...
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    90: 49 8f 49 8d ff ff 49 8f 00 00 00 00 00 00 00 00 I?I?..I?........
    a0: 00 00 00 00 00 1c 00 00 00 00 00 00 00 00 00 00 .....?..........
    b0: 1c 3a 14 08 25 00 18 00 88 33 83 74 80 00 00 00 ?:??%.?.?3?t?...
    c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    d0: 00 43 94 04 60 f2 00 02 00 00 00 10 00 00 00 00 .C??`?.?...?....
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    f0: 5f 55 42 39 36 30 00 00 00 00 00 00 00 00 00 00 _UB960..........

    ps> Des chip (964> 960) have been changed.
    The print on the chip was 960, but it seems to be a problem.

    Regard

    CHOI

  • 0 in reply to CHOI KILSOO
    Prodigy 180 points

    Additional question.

    To set up as shown above

    -----------------------------------------------

    print "*** RX0 VC=0 ***"
    board.WriteReg(0x4C,0x01) # RX0
    board.WriteReg(0x70,0x1F) # VC0

    # print "*** RX1 VC=2 ***"
    board.WriteReg(0x4C,0x12) # RX1
    board.WriteReg(0x70,0x9F) # VC2

    -------------------------------------------------

    Is this right?

  • 0 in reply to CHOI KILSOO
    TI__Expert 3390 points
    Do you have any input CSI limitations on your SoC? If setting 0x1F = 0x00 on the 960 is causing issues then it's possible that the SoC can't handle 1.6G/lane of data. Can you confirm? Does setting 0x1F = 0x02 have any issues?

    This is not correct, Register 0x71 and 0x72 are there for when the DS90UB960-Q1 is in backwards compatiblity mode and is configured for RAW operation. When using the DS90UB953-Q1 with the 960, you are always in CSI mode. The only register that you need to configure is 0x72 on the 960. That register is used to configure the Virtual Channels. If both of the sensors coming in have a VC of 0 then set 0x72 = 0xE4 for Rx0 and 0xEA for Rx1. This will set the VC of 0 for Rx0 to VC= 0 and VC of 0 for Rx1 to VC=2. If the incoming VC's are not 0, then please set register 0x72 accordingly to that.
    print "*** RX0 VC=0 ***"
    board.WriteReg(0x4C,0x01) # RX0
    board.WriteReg(0x72,0xE4) # VC0

    # print "*** RX1 VC=2 ***"
    board.WriteReg(0x4C,0x12) # RX1
    board.WriteReg(0x72,0xEA) # VC2
  • 0 in reply to Mandeep S
    Prodigy 180 points

    HI

    I checked again.
    There is no problem even if 0x0f = 0x00 (1600).
    0x0f = 0x02 (800) There is also no problem.
    But still
    rx0,1 -> csi port does not work with 0.
    Data can not be measured when checked with an oscilloscope.

    rx0 -> csi port 0, rx1 -> cxi port 1 will work fine at the same time.


    I set it up as follows

    ------------------------------------------------------

      #print "*** RX0 VC = 0 ***"
      board.WriteReg (0x4C, 0x01) # RX0
      board.WriteReg (0x72,0xE4) # VC0

      # print "*** RX1 VC = 2 ***"
      board.WriteReg (0x4C, 0x12) # RX1
      board.WriteReg (0x72,0xEA) # VC2

      # board.WriteReg (0x1f, 0x02) # 800 clock
      board.WriteReg (0x1f, 0x00) # 1600 clock

      board.WriteReg (0x21,0x3c) # "*** line concatenation ***"

      board.WriteReg (0x33,0x01) # 4lane

      board.WriteReg (0x20,0xcc) # rx 0,1 to csi 0

    ------------------------------------------------------

    0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
    00: 60 00 1e 40 d0 01 00 fe 1c 10 7a 7a 0f 09 00 ff `.?@??.???zz??..
    10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 ..............?.
    20: 0c 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ?<..............
    30: 00 00 01 01 00 00 00 03 00 00 00 00 00 00 00 00 ..??...?........
    40: 00 a9 71 01 00 00 20 00 00 00 00 12 12 53 5d 64 .?q?.. ....??S]d
    50: 00 00 00 04 06 00 00 00 5e 00 00 30 1a 50 00 00 ...??...^..0?P..
    60: 00 00 00 00 00 52 00 00 00 00 00 00 00 78 88 88 .....R.......x??
    70: 6b 6c ea 04 38 0f 00 c5 00 01 02 02 20 00 00 00 kl??8?.?.??? ...
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    90: 1c 05 1c 03 ff ff 1c 05 00 00 00 00 00 00 00 00 ????..??........
    a0: 00 00 00 00 00 1c 00 00 00 00 00 00 00 00 00 00 .....?..........
    b0: 1c 3a 14 08 25 00 18 00 88 33 83 74 80 00 00 00 ?:??%.?.?3?t?...
    c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    d0: 00 43 94 03 60 f2 00 02 00 00 00 10 00 00 00 00 .C??`?.?...?....
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    f0: 5f 55 42 39 36 30 00 00 00 00 00 00 00 00 00 00 _UB960..........

    ------------------------------------------------------

    Regards

    Choi

  • 0 in reply to CHOI KILSOO
    TI__Expert 3390 points

    Hi Choi,

    I noitced you are not providing a framesync signal unless it's external. If you are not, can you please follow the example in the DS90UB960-Q1 Datasheet section 7.4.24.2.1 to enable the internal framesync.

    Additionally, as a reference, when enabling/disabling CSI transmitters, you should be following the procedure in section 7.4.25.8 to avoid any issues.

    Regards,
    Mandeep Singh