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Original question:

SN65HVD73: Dual channel

SN65C1167E: Behavior of DE pin in open

Liu Yang
Expert 5935 points
Part Number: SN65C1167E

Hi Team,

Please help me answer the follow question from my customer, thank you so much.

Q1.If 12pin (DE) of SN65C1167EPW is Open,
      how does SN65C1167EPW work?
      (Does the Drive circuit become effective?)

Q2.If the Device connected to the 12 pin (DE) of the SN65C1167EPW is high impedance,
      How does the SN65C1167EPW work?
      (There is no external pull-down resistor etc.)
      (Does the Drive circuit become effective?)

Best Regards,
Tom Liu

  • 0
    TI__Guru 62910 points

    Hi Tom,

    The DE pin of this device does not have an integrated pull-up or pull-down, and so in either case (left open or connected to a high-Z output) the logic state of the pin would be undefined.  The pin voltage would be determined primarily by PCB leakages or coupled noise, and the driver could be either enabled or disabled based on this pin voltage.  To avoid this undetermined behavior, I recommend placing a pull-down resistance on the DE pin so that it is only enabled when the pin is intentionally driven (by a control line from an MCU, UART, etc.).

    Regards,
    Max

  • 0 in reply to Max Robertson
    TI__Expert 5935 points

    Hi Max,

    Thank you for your answer. But my customer has additional question could you please see it?

    Dose "PCB leakages" mean leakage current?
    The leakage current of the IC (FPGA) connected was -10uA/+10uA.
    Can you tell me the voltage of the DE pin from this leak current?
    (If leakage current * R = V, how is R decided?)
    Also, if the voltage between the data sheet VIH = min 2v and VIL = max 0.8V(for example 1.5v)
    how does DE work?

    By the way below is the background
    Currently we are scheduled to pull down the DE pin by jumper.
    Because we need to explain the current state to the user
    I asked the question above.

    Best Regards,
    Tom Liu

  • 0 in reply to Liu Yang
    TI__Expert 5935 points

    Hi Max,

    Maybe the additional question is difficult to answer,
    but my customer has to explain it to users, so I need your help.

    Best Regards,
    Tom Liu

  • 0 in reply to Liu Yang
    TI__Guru 62910 points

    Tom,

    Yes, I was referring to leakage currents that could be present on the application board.  You could also think of these as weak resistances between the signal line and other signals like VCC or ground.  For example, the DE pin of this device is specified to sink at most 1 uA when VCC or VIH is applied to it.  That suggests a minimum input resistance of 2 V / 1 uA = 2 MOhm to ground.  It is also specified to source up to 1 uA when the input is grounded; that suggests a minimum input resistance of 5.5 V / 1 uA = 5.5 MOhm to VCC.  You could consider these the "R" values in your equation.

    It seems like the FPGA leakage current is specified higher at 10 uA, but that the polarity could be either negative (sourcing) or positive (sinking).  If there are no other leakage sources besides the FPGA and the transceiver, then when the FPGA sources 10 uA the DE voltage would be high and when the FPGA sinks 10 uA the DE voltage would be low.  Please let me know if this does not make sense.

    The DE threshold voltage will be somewhere between 0.8 V and 2 V.  (Per the datasheet specifications, it could be considered anywhere within this range and may vary within the range from to device to device and over different operation conditions.)  If, for example, the input threshold were 1.5 V, then 1.4 V would be considered "low" and 1.6 V would be considered "high."

    Regards,
    Max