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DS90UB953-Q1: DS90UB953-Q1 registers write fail when generate test pattern

孙百勋
Prodigy 50 points
Part Number: DS90UB953-Q1
Other Parts Discussed in Thread: ALP

According to datasheet, the test pattern is generated by reading and writing i2c to three registers 0xB0,0xB1 and 0xB2. However, after the success of writing data 0x01 to IND_ACC_ADDR (0xB1), the chip cannot read or write to any register, and can only read or write to the register after repowering (using pin PDB). The same IND_ACC_ADDR (0xB1) writes data 0x02 without affecting the read and write of other registers. What's the reason, please

  • 0
    TI__Prodigy 460 points

    Hello 孙百勋,

    Could you clarify the following:

    a.) Are you using a 953 EVM board?

    b.) Are you using ALP(Analog Launch Pad) for setting your registers?

    Best,

     

    Liban H.

  • 0 in reply to Liban Hussein1
    Prodigy 50 points

    Hello Liban

    I used my own design board

    Now I know where I went wrong. It was a stupid mistake. I used the 16-bit i2c address, which caused 953 to be written down. The test pattern is now ready for production.

    Now there is a new problem, how to set the FV/LV polarity of the test pattern generated by 953？

    thanks.

  • 0 in reply to 孙百勋
    TI__Guru** 103215 points

    Hello,

    The FV/LV polarities only matter if connected in backward compatibility (DVP mode) to an older deserializer. In CSI-2 mode, the HSYNC and VSYNC signals are generated from sync packets. 

    If you are in DVP mode, then you can control the FV/LV polarity with register 0x10.

    Best Regards,

    Casey