TCA9517-Q1: I2C signal of B-side input waveform question

user6013811

Part Number: TCA9517-Q1

Hi,

We have a 3.3V and 1.8V I2C Level shift design in our project, 3.3V is master at the B-side, 1.8V is slave at the A-side.

I saw the non monotonic waveform at the B-side input measurement. (please refer below)

Why does the input voltage keep a period of about 0.5V voltage before rise to 3.3V high?

Thank you.

Frank

over 5 years ago

0 BOBBY over 5 years ago

TI__Guru 60980 points

Hey Frank,

This is normal/expected behavior when you are driving the B side and releasing. This is a 'side effect' of how static voltage offset buffers work. The B side waits (sits at ~500mV) until the A side goes above a certain threshold voltage before it releases.

Is the customer seeing any I2C errors due to this? I haven't seen a case where this has caused problems yet.

-Bobby

0 Miguel Robertson over 5 years ago in reply to BOBBY

TI__Guru 62920 points

Hi Frank,

I just wanted to add that if you would like to read more about how I2C buffers operate you may want to reference this application note:

http://www.ti.com/lit/an/scpa054/scpa054.pdf

Regards,
Max

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TCA9517-Q1: I2C signal of B-side input waveform question