TLK10031: Could you give instruction guide for setting up XAUI to SFI/XFI configuration on TLK10031?

Hi,

When using this TLK device as a XAUI-to-SFI PHY, the same line-rate/PLL/ref_clk settings apply as for the XAUI-to-KR PHY case. Indeed you would want to disable the auto-neg and link training when supporting SFI/XFI optical interfaces. Otherwise, other settings are same. The REF_CLK should be either 156.25MHz or 312.5MHz. See excerpt below from the datasheet.

7.3.16 10GBASE-KR Line Rate, PLL Settings, and Reference Clock Selection

The TLK10031 includes internal low-jitter high quality oscillators that are used as frequency multipliers for the low speed and high speed SERDES and other internal circuits of the device. Specific MDIO registers are available for SERDES rate and PLL multiplier selection to match line rates and reference clock (REFCLK0/1) frequencies for various applications.

The external differential reference clock has a large operating frequency range allowing support for many different applications. A low-jitter reference clock should be used, and its frequency accuracy should be within ±200 PPM of the incoming serial data rate (±100 PPM of nominal data rate).

When the TLK10031 device is set to operate in the 10GBASE-KR mode with a low speed side line rate of 3.125 Gbps and a high speed side line rate of 10.3125 Gbps, the reference clock choices are as shown in Table 7-1. In general, using a higher reference clock frequency results in improved jitter performance.

Table 7-1. Specific Line Rate and Reference Clock Selection for the 10GBASE-KR Mode:

Cordially,

Rodrigo Natal

HSSC Applications Engineer