DP83867IRPAP-EVM: Compliance test for DP83867IRPAP-EVM

Hi Kenshow,

DP83867IRPAP does pass compliance test. Has customer followed all the register settings from the compliance testing appnote?

-Regards

Aniruddha

Hi Aniruddha,

 DP83867ERGZ-R-EVM was introduced in the TI's training video, so we knew that it passed the compliance test, and this time we could know that DP83867IRPAP-EVM also passed. Thank you very much.

 On the customer side, register settings are set according to the application note. Since other tests (such as the Template test) of test signal 1 have passed, we believe that there is no problem with the settings.

In the customer's DP83867IRPAP-EVM, VCC_IO uses the external power supply 3.3V (controller side) to check the PHY register. Could you give me any advice on what should be noted here?

Best regards,
Kenshow

Hi Kenshow,

I would suggest reading back the registers to make sure that the changes have taken place. Also, for compliance testing very short cable length should be used i.e. 1-2inches. Long cable length can cause compliance issues.

-Regards

Aniruddha

Hi Aniruddha,

The measurement environment was the same as Figure 1 of application note SNLA239A. The cable was short.

After writing the mode 1 settings with a script according to the application note, I read the DP83867IRPAP-EVM register settings. So, I noticed the address 0x01D5 was 0x0000. Any other registers were set correctly. Was this EVM configured correctly?

However, in DP83867ERGZ-R-EVM returns 0xF508.

What is the difference between these two boards?

Best regards,
Kenshow

Hi Aniruddha,

 I found that the reserved bit is set  in  DP83867IRPAP-EVM as follows:

Address 0x006E is: 0x0000.
Address 0x006F is: 0x0100.

Bit[8] is set. Is it normal?

Anyway, writing the value 0x1F508 to the address 0x01D5 register of DP83867IRPAP-EVM returns 0x000, so I want to know how to write it correctly.

I am using with USB-2-MDIO Tool and MSP-EXP430G2 to read/write the EVM.

Best Regards,
Kenshow

Hi,

Is there any update about the inability to write to the register address, 0x01D5 on EVM?

I am waiting for your reply.

Best Regards,
Kenshow

Hi kenshow,

Register 0x1D5 is applicable to the 48pin QFN devices. Its a Read Only register for 64pin QFP devices. So it is ok if you are reading 0x0000 on the DP83867IR-PAP EVM. Can you test each channel individually? You can enable test mode on each channel by changing register 0x25 as follows.

0x25 =0x0400 for Channel A

0x25 =0x0420 for Channel B

0x25 =0x0440 for Channel C

0x25 =0x0460 for Channel D

-Regards

Aniruddha

Hi Aniruddha,

We checked by setting register address 0x25. 

However, there was no improvement in the waveform.

Begards,
Kenshow