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SN65DSI86: Some quesitons

Shu-Cheng LIN
Guru 11785 points
Part Number: SN65DSI86
Other Parts Discussed in Thread: TEST2

Hi Sirs,

Sorry to bother you.

We have one question need your support.

 

We used the IC of TI SN65DSI86 for DSI to DP, and I check the Specifications that there two ways can be used of PLL.

  1. Oscillator connector REFCLK and setting by I2C or GPIO
  2. Feeding the DACP/N to instead of REFCLK.

 

If I want to use the second way of DACP/N, is there any recommendation you can suggest us.

Is there any setting need software support?

Our schematic as below

DSI86.pdf

  • 0
    TI__Guru**** 182211 points

    Shu-Cheng

    Please note the limitation when using DACP/N as the clock source.

    When using the REFCLK as the clock source, any DSI Clock frequency is supported, but if the clock source was instead the DSI A clock, then the required DSI Clock frequency would need to change to a frequency supported by the DSI86. When operating in this mode, any one of the following DSI A clock frequencies can be used: 384 MHz, 416 MHz, 460.8 MHz, 468 MHz, or 486 MHz. 

    On the schematic

    Are you AC coupling the eDP interface, both the main link and the AUX channel?

    You have one signal labeled eDP3P, is this a typo?

    You may want to add a cap on the EN pin, please see section 8.4.1.

    Please have the option of TEST2 being pulled up to VCCIO

    You may want to provide pullup option for the GPIO pins.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Guru 11785 points

    Hi Sirs,

    Thanks for your reply.

    I had designed the TI display solutions one is TI_SN65DSI84ZQER and another is TI_SN65DSI86ZQER.

    Please help me to insure the schematic correct.

    The red word is my reply.

    Schematic:

    MINI DS.pdf

     

    Are you AC coupling the eDP interface, both the main link and the AUX channel?

    This is the Module board and the AC coupling are designed in carried board.

    You have one signal labeled eDP3P, is this a typo?

    Yes, I type wrong word and thank you.

    You may want to add a cap on the EN pin, please see section 8.4.1.

    I connect EN with the system reset pin, as I check the chapter we need to ensure the VCC was ramp up stable before EN released.

    Please have the option of TEST2 being pulled up to VCCIO

    According the description, TEST2 pull high is for internal test.

    Why you want me pull this pin to high?

     You may want to provide pullup option for the GPIO pins.

    I change the GPIO for configuration.

  • 0 in reply to Shu-Cheng LIN
    TI__Guru**** 182211 points

    Shu-Cheng

    1. Please make sure you have pullup on SCL and SDA for the I2C communication.

    2. TEST2 needs to be pulled high in order for the SW to disable panel that does not support ASSR.

    3. Please make sure AUX is AC coupled, pullup/pulldown is needed for DP, optional for eDP

    4. You have both DSI84 and DSI86 ADDR pulled to GND, this means they will share the same I2C address, is this intended?

    Thanks

    David

  • 0 in reply to Shu-Cheng LIN
    TI__Mastermind 35130 points

    Hi Shu-Cheng,

    For the DSI84, please note that VCORE is an output and not an input. Namely, a voltage source should not be connected to this pin. Also, why are there 0R resistors on only LVDS channel A and not LVDS channel B? 

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Guru 11785 points

    Hi Sirs,

    Thanks for your reply.

    For the DSI84 question, I add 0R in the channel A for co-layout with DSI output. You can find the 0R between MIPI_DSI and channel A.