Other Parts Discussed in Thread: TLK10232, TLK10034
Hi
Could you let me some advice for XAUI to SFI/XFI?
I already referred to https://e2e.ti.com/support/interface/f/138/p/760354/2852936?tisearch=e2e-sitesearch&keymatch=TLK10031#2852936 in order to configure XAUI to XFI.
But LS_PLL_LOCK and HS_PLL_LOCK field indicated PLL-unlock.
So I'd like to get some advice about setting up. while debugging problem, I dobule checked hardware strapping for 10G-KR( MODE_SEL, 1E.0001 bit 10 in accordance with Table 7-2).
Current MODE_SEL is set to PD.
Q1) CHANNEL_CONTROL_1 :
the default value of This register is 0x0B24. What is right value of SW_PCS_SEL & SW_DEV_MODE_SEL for XAUI to XFI/SFI? I tried 0x324 or 0x724 to CHANNEL_CONTROL_1
Q2) HS_CH_CONTROL_1 (register = 0x001D) (default = 0x0000) (device address: 0x1E)
According to the description of bit [13:12], REFCLK_FREQ_SEL_1,REFCLK_FREQ_SEL_0, HS_PLL_MULT,LS_MPY field on 1E.0002, 1E0003 must be set up automatically.
when I read two register, HS_PLL_MULT field had 0xD. but Accoriding to Table 7-1, It should have 0xC for 16.5 multiplier. Do you think which one affected default vaule of HS_PLL_MULT(0x0D)?
When user wants to apply manual setting according description on REFCLK_FREG_SEL1, Is there any specific necessary sequence?
Q3) Does link status on HS, LS Interface affect LS_PLL_LOCK and HS_PLL_LOCK 's value?
appreciate your help in advacne.
thank you
Best Regards