Hi,
I was referring to Thread ID#839805 & i'm having further questions with regards to this topic. I'm attempting to modify my design with following setups & whether my XIO2001 will still power-down properly?
1. upon power-down sequence, if both (assert PERST) & (REFCLK removed) simultaneously will i crash my power-down sequence?
2. VDD_15, ADD_33 and PCIR are turned off almost simultaneously together (+-2ms apart) in no specific order. (Note: power rails turn 60ms after PERST and REFCLK turn off)
Appreciate some advise feed for this query. Thanks.
Regards,
Leo
