DP83865: Transmit FIFO error (0x11,9)

user6247700

Prodigy 30 points

Part Number: DP83865
Other Parts Discussed in Thread: AM3352

Hello,

I'm using DP83865 on a custom board with AM3352 chip.

The PHY can be link up state in 100Mbps full duplex mode and transmit data.

But the data transmitted from the PHY misses some bits at a certain interval.

And I found that Transmit FIFO error (0x11,9) bit be set after data transmitted.

So now questions:

* What does the state mean? Why the error happens? I can't find details from datasheet.

* How shoud I deal with this situation? I want to transmit data without the bit be set (FIFO error) and missing bits.

I'm sorry for my unskillful English.

Thank you,

Best regards,

Koki Inoue

over 4 years ago

0 Cecilia Reyes over 4 years ago

TI__Genius 9920 points

Hi Koki,

Do you have your schematic for your design? Typically this part is not used for new designs. We have the DP83867 if you are interested in that.

Thanks,

Cecilia

0 user6247700 over 4 years ago in reply to Cecilia Reyes

Prodigy 30 points

Hi Cecilia,

Thank you for your reply.

I cannot get schematic, sorry.

I just want to know what happens and why, and I want to transmit data with DP83865.

Do you have some advice without schematic?

Thank you,

Koki

0 Cecilia Reyes over 4 years ago in reply to user6247700

TI__Genius 9920 points

Hi Koki,

Per the datasheet it states:

Transmit FIFO Error: Indicates whether a FIFO overflow or underrun has occured. This bit is cleared every time link is lost.

It appears that the error is occurring because a link is lost between the PHY and the AM3352.

0 user6247700 over 4 years ago in reply to Cecilia Reyes

Prodigy 30 points

Hi Ceciia,

Thanks for your reply.

In my situation, Transmit FIFO Error bit "is set"(=1), not is cleared(=0).

And I confirmed that the bit is cleared when I have link be down.

Thank you,

Koki

0 Cecilia Reyes over 4 years ago in reply to user6247700

TI__Genius 9920 points

Hi Koki,

Could you explain what you mean when you say "the link is down" are you saying the bit is cleared to = 0 when there is not link between the two devices?

Thanks,

Cecilia

0 Cecilia Reyes over 4 years ago in reply to Cecilia Reyes

TI__Genius 9920 points

Hi Koki,

One more thing to add:

Could you perform a test in Loopback mode to confirm you are still receiving errors and to see if still continue to receive missing bits from the Tx side?

Thanks,

Cecilia

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DP83865: Transmit FIFO error (0x11,9)