Hi Sir,
Once external voltage shorting to data lines(VD+ or VD-)above OVP threshold is detected by IC, it shuts off its FET inside.
Above situation, VD+/VD- will connect to where inside IC? And will VD+/VD- draw current from external voltage?
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Hi Sir,
Once external voltage shorting to data lines(VD+ or VD-)above OVP threshold is detected by IC, it shuts off its FET inside.
Above situation, VD+/VD- will connect to where inside IC? And will VD+/VD- draw current from external voltage?
Hi Anne,
When the OVP happen in the data line. The internal data switch between VD+/- and D+/- will be turn off to protect the D+/- side SOC system.
VD+/- internal is connect to data switch FET drain side.The VD+/- side high voltage will not draw current from external during OVP happen.
Hi Anne,
No, the internal OVP FET will switch off in very short time typical about 200nS.
Hi Michael,
Since customer is looking for the root cause why U61 pin2/3 will burn to short,
So need our help to clarify if TDP3S714-Q1 both Vbus_sys and Vin are off and there is a voltage input to U61 pin2 more around 12V,
Is there any possible that TDP3S714-Q1 pin5 VDP internal short to GND?
Thanks
Hi Anne,
The VDP internal is the ESD clamp ,the ESD current will go through the VDP to the ground once the VDP internal ESD clamp circuit be actived.