TLK10031: TLK10031 HS Interface Packet loss (HS_ERR_COUNT is increased)

lee jw

Part Number: TLK10031

Hi Team.

I am using tlk10031.

High speed interface is XFI and low speed interface is AXUI.

However, PACKET LOSS occurs in the RX direction of the high speed interface. (HS_ERR_COUNT [15: 0] has been increased.)

We have reduced the packet loss by setting two registers. So,The packet loss occurs 2 ~ 3 pcs in about 60 hours.

Two register and value is as follows.

HS_CDRFMULT -> 00
HS_CDRTHR -> 11

What does it mean that packet loss is reduced by register setting in signal integrity side?

What registers should be set more to improve packet loss? (There should be no packet loss.)

thakns

0 Rodrigo Natal over 4 years ago

Hi,

What does it mean that packet loss is reduced by register setting in signal integrity side?

This might mean that the TLK inut signal jitter is high. Do you have a jitter decomposition for the 10G input signal to TLK?

What registers should be set more to improve packet loss? (There should be no packet loss.)

I would suggest to try tuning the TLK HS_EQPRE[2:0] and HS_LOOP_BANDWIDTH[1:0] parameters. See tables below from the datasheet.

Table 7-14. HS_SERDES_CONTROL_1 Field Description

Bit	Field	Type	Reset	Description
15:10				For TI use only (Default 6’b100000)
9:8	HS_LOOP_BANDWIDTH[1:0] (RXG)	R/W		HS Serdes PLL Loop Bandwidth settings 00 = Medium Bandwidth 01 = Low Bandwidth 10 = High Bandwidth 11 = Ultra High Bandwidth. (Default 2'b11)
7	RESERVED	R/W		For TI use only (Default 1’b0)
6	HS_VRANGE (RXG)	R/W		HS Serdes PLL VCO range selection. 0 = VCO runs at higher end of frequency range (Default 1’b0) 1 = VCO runs at lower end of frequency range This bit needs to be set HIGH if VCO frequency (REFCLK *HS_PLL_MULT) is below 2.5 GHz.
5	RESERVED	R/W		For TI use only (Default 1’b0)
4	HS_ENPLL (RXG)	R/W		HS Serdes PLL enable control. HS Serdes PLL is automatically disabled when PD_TRXx_N is asserted LOW or when register bit 1E.0001 bit 15 is set HIGH. 0 = Disables PLL in HS serdes 1 = Enables PLL in HS serdes (Default 1’b1)
3:0	HS_PLL_MULT[3:0] (RXG)	R/W		HS Serdes PLL multiplier setting (Default 4’b1101). Refer : Table 7-15 HS PLL multiplier control

Table 7-18. HS_SERDES_CONTROL_3 Field Description

Bit	Field	Type	Reset	Description
15	HS_ENTRACK (RXG)	R/W		HSRX ADC Track mode. 0 = Normal operation (Default 1’b0) 1 = Forces ADC into track mode
14:12	HS_EQPRE[2:0] (RXG)	R/W		Serdes Rx precursor equalizer selection 000 = 1/9 cursor amplitude 001 = 3/9 cursor amplitude (Default 3’b001) 010 = 5/9 cursor amplitude 011 = 7/9 cursor amplitude 100 = 9/9 cursor amplitude 101 = 11/9 cursor amplitude 110 = 13/9 cursor amplitude 111 = Disable
11:10	HS_CDRFMULT[1:0] (RXG)	R/W		Clock data recovery algorithm frequency multiplication selection (Default 2'b01) 00 =First order. Frequency offset tracking disabled 01 = Second order. 1x mode 10 = Second order. 2x mode 11 = Reserved
9:8	HS_CDRTHR[1:0] (RXG)	R/W		Clock data recovery algorithm threshold selection (Default 2'b01) 00 = Four vote threshold 01 = Eight vote threshold 10 = Sixteen vote threshold 11 = Thirty two vote threshold

Cordially,

Rodrigo Natal

HSSC Applications Engineer

0 lee jw over 4 years ago in reply to Rodrigo Natal

Hi,

thanks for your Reply

I tried the Register you gave me.

I knew the following information.

1. TLK HS_EQPRE [2: 0] worked best at "000". However, packet loss has not been resolved.

2. HS_LOOP_BANDWIDTH [1: 0] had no effect.

Can you advise me to solve the problem with the above result?

0 Rodrigo Natal over 4 years ago in reply to lee jw

Hi,

What are the Tx output amplitude and de-emphasis settings being used for signal input to TLK device? Can these Tx settings be tuned?

Cordially,

Rodrigo Natal

HSSC Applications Engineer

Interface forum