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DP83869HM: Strap setting is not recognized, registers readback fail

Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869

Hello,

I have a custom design and I am struggling to get the data link. The PHY and network card can detect cable and link, but cannot send the data (get IP from DHCP or perform ping).

DP83869HM is used to interface with Fiber SFP module. The RGMII interface is connected to LAN7801 that is connected to computer via USB. I can access the PHY (DP83869HM) registers through command line interface from win 10. I read PHYIDR1 0x2 register well with value 0x2000. The SFP modules and cable were verified on different devices.
The current state is, that link is up what I can see from computer that design is connected to and also from router with another SFP module. The router is set up to auto-negotiation for all modes 10M to 1G.

Here are my questions:

1. A potential issue might be with detecting strapping option. I have the setting for RGMII to 1000Base-X with autonegotiation on and LOS detection on (JTAG_TDO pin - 2.5k pullup, RX_D3 open, RX_D2 open, LED_0 - pulldown, LED_1 - pullup), but I read 0x0000 from 0x6E register. What could be reason for wrong detection of strapping options?

2. I suspect that RGMII might not be configured properly: MAC IC (LAN7801) has RGMII version 2. I measure 125MHz on RGMII TX and RX clock signals. I also see some data on RX and TX bus seconds after power-up. DP83869HM has RGMII delay enabled as default after reset 0x32 register value is 0x0000 (correct). The ANA_RGMII_DLL_CTR 0x86 register holds 0x0004 (should be default 0x77). After successful write of 0x77, I read back again 0x0004. Why is there a different default value after reset and why I cannot change the value?

3. Document DP83869 1000Base-X Link Detection states that "link status is stored in the FX_STS register bit [1]" whereas DP83869 datasheet says it is bit[2] of the FX_STS register. Is link status bit 1 or bit 2 in FX_STS register? If it is bit 2 then I read LINK STATUS BIT = 1, SERDES SYNC STATUS BIT = 0, what is stated as "not applicable" in link detection document.

     

4. I am not able to download USB2MDIO GUI tool that works on launchpad. Is it freely available for download anywhere? It might help with a debug.

Do you please have some ideas what I can be missing and how I can make the design operational?

Please find the schematics excerpt and PHY register damp after power up below.


Schematics excerpt:

RGMII is connected to MAC LAN7801. MAC has reset output connected to PHY RESET_N.

PHY registers after power up and recognized link:

address : value
0x0000 :0x1000
0x0001 :0x616d
0x0002 :0x2000
0x0003 :0xa0f1
0x0004 :0x05e0
0x0005 :0x4060
0x0006 :0x0007
0x0007 :0x2001
0x0008 :0x0000
0x0009 :0x0200
0x000A :0x0000
0x000D :0x4007
0x000E :0x0000
0x000F :0xf000
0x0010 :0x5448
0x0011 :0xac02
0x0012 :0x0000
0x0013 :0x0400
0x0014 :0x29c7
0x0015 :0x0000
0x0016 :0x0000
0x0017 :0x0040
0x0018 :0x6150
0x0019 :0x4404
0x001A :0x0002
0x001E :0x0012
0x001F :0x0000
0x0025 :0x4060
0x002C :0x0000
0x002D :0x4007
0x002E :0x0000
0x0031 :0xac02
0x0032 :0x0000
0x0033 :0x0000
0x0037 :0x0040
0x0039 :0x4404
0x003A :0x0002
0x0043 :0xa0f1
0x004F :0xf000
0x006E :0x0000
0x0086 :0x0005
0x0134 :0x29c7
0x0135 :0x0000
0x0170 :0x5448
0x0180 :0x1000
0x0181 :0x616d
0x0182 :0x2000
0x0183 :0xa0f1
0x0184 :0x05e0
0x0185 :0x4060
0x0190 :0x5448
0x0191 :0xac02
0x0192 :0x0000
0x0193 :0x0000
0x0194 :0x29c7
0x0195 :0x0000
0x0196 :0x0000
0x0197 :0x0040
0x0198 :0x6150
0x0199 :0x4404
0x01A4 :0x05e0
0x01A5 :0x4060
0x01A6 :0x0005
0x01DF :0x0000
0x01E0 :0x1000
0x0C00 :0x1000
0x0C01 :0x616d
0x0C02 :0x2000
0x0C03 :0xa0f1
0x0C04 :0x05e0
0x0C05 :0x4060
0x0C06 :0x0005
0x0C07 :0x2001
0x0C08 :0x0000
0x0C18 :0x6150
0x0C19 :0x4404

  • Hi Jurag,

    I have started looking into this. At first look it looks like that your register reads are not working fine. For example, I see that register 0001 = 616D after power up but in datasheet I see that value of bits [15:12] can not be different from 0111. Lets clean up the register read/write operation first so that we can rely on it for checking status of phy. Let me know the following for this :

    1. Are you using 25MHz clock from crystal or some other source? I see both in the schematic.

    2. If not crystal, then is this clock active before the power of 869 is up?

    3. What is the MDC clock frequency? Is if free running or does it stop after each register read?

    Also on LED pins I see two options of LEDs. Which one was is finally populated?

    Usb2mdio link : http://www.ti.com/tool/USB-2-MDIO

    --

    Regards,

    Vikram

  • Thank you for your reply Vikram,

    The register 0x01 reports 0x6169 after power up and in a second it changes to 0x616d - probably making a link when optical cable is inserted.

    1. Yes, I am using 25MHz crystal directly connected to PHY IC.

    2. Crystal is operating normally; I can measure the 25MHz waveform.

    3. MDC signal shows clock bursts about every second, or more often if I am configuring anything through CLI or in windows. MDC frequency is 2.5MHz. You can find scope screenshots below. This is probably some periodic link-check.

    I exported better schematics with variant assembly. You can see exactly what is populated at my current sample. I removed LEDs just in case they would interfere with STRAP setting.
    I am still not able to download USB2MDIO tool. It reports "Sorry, the page you’re looking for can’t be found." after I sign in and try to download by "request" button.

    Scope screenshots: 

    detail:

    Do you have any ideas what else I could try? 
    Your support is appreciated.

    sch-variant-assembly-conpc008.pdf

  • Hi Juraj,

    Here is what I can conclude so far :

    1. Your straps are in correct mode by straps : Rgmii to Fiber.

    a. Because Rgmii lines are toggling : both clock (125MHz) and data are toggling. Without Rgmii mode entry they will not toggle.

    b. Fiber link is up with link-partner.

    2. Register read writes has some issue :

    a. 0x0001[15:11] should always be 0111.

    b. When you are trying to write register to program delay , readback is showing incorrect value.

    3. Rgmii data transfer to MAC is not successful because most likely you are not able to program the delay correctly (register write issue).

    I guess you tried the link I sent over for downloading usb2mdio. Can you raise query for the same? I am not sure how to resolve the download issue but related team will be able to help you faster.

    Also is there any other device connected on the same mdc-mdio bus? If yes, can we power down those devices and see if then controller can talk better with phy? (To rule out any clash)

    --

    Regards,

    Vikram

  • Hello Vikram,

    you are correct in all the points. That is the scenario I see. 

    The register access for some registers does not operate properly. However some registers are acting normally - I  can turn on/off 25MHz clock pin output and measure - it is reacting to changes well.

    I will create a new post related to USB2MDIO.

    There is only LAN7801 IC interconnected with DP83869HM IC using mdc-mdio bus. They are interconnected directly through 0R resistors. Additionally MDIO has 1.5k pullup to 1V8 level (I tried 2k2 and 1k5).

    I am also testing this on 2 boards and they are acting the same.


    Are there any other things I could check?
    Thanks,

    Juraj

  • Hi Jurag,

    Let me know if you were able to figure out usb2mdio for debug.

    --

    Regards,

    Vikram

  • Hello Vikram,

    I tried using USB2MDIO tool to read registers:
    With extended register setting turned on:

    Register 0000 is: 1140 
    Register 0001 is: 616D 
    Register 006E is: 0204 
    Register 01DF is: 0041 
    Register 0032 is: 00D0 
    Register 0086 is: 0077 
    Register 0C00 is: 1140 
    Register 0C01 is: 616D 
    Register 0000 is: 1140

    and with the extended register setting off:

    Register 0000 is: 1140 
    Register 0001 is: 616D 
    Register 006E is: 1140 
    Register 01DF is: F000 
    Register 0032 is: 2000 
    Register 0086 is: 0007 
    Register 0C00 is: 1140 
    Register 0C01 is: 616D 
    Register 0000 is: 1140

    Some register values are different. I guess registers with address higher than 0xE need to be read with extended register setting on. 

    Moreover, when I disconnected MDC MDIO connection between by MAC and PHY and set up RGMII delay (PHY enabled on TX and RX as default and turned off on MAC), it started working. I got data connection and working ping.

    One more thing is bothering me in the design. The MAC and operating system cannot tell the link status of PHY because the MDC MDIO is disconnected and always assumes that cable is connected. 

    If MDC and MDIO is connected, I can see cable connection status, but I have no data - original problem.

    I connected a scope to MDC and MDIO and decoded the communication between MAC and PHY:

    1. after power up MAC scans all the PHY addresses and tries to red 0x01 register until it finds PHY

    2. reads reg 0x01 val 0x616D

    3. reads reg 0x01 val 0x616D

    4. reads 0x02  - 0x2000

    5. reads 0x03 - 0xA0F1

    6. reads 0x04 - 0x0020

    7. writes 0x04 - 0x0AE0

    8. reads 0x9 - 0x1300 

    9. writes 0x9 - 0x0200, 1G FD, auto master/slave

    10. writes:
    0xD - 0x0003

    0xE - 0x003C

    0xD - 0x4003

    0xE - 0x0060

    11. writes to 0x0 - 0x1200 - autonegotiaion restart

    I do understand some of these commands, but I do not know what changes after point 10, and value of point 6.

    Thank you for checking this.
    Juraj

  • Hi Juraj,

    I am not sure whether I understood the present debug status correctly. Were you able to figure out :

    1. Why MAC turning-off/on + MDC/MDIO disconnected is correcting the problem? Is it a MAC issue?

    2. Do you need help to how to read/write extended register (with address greater than 1F) ? Here is an example to read lets say write reg<0x0123> of mmd 1F = 0xA0A0 :

    000D 001F

    000E <reg_address>

    000D 401F

    000E <value>

    To read :

    000D 001F

    000E <reg_address>

    000D 401F

    000E

    Let me know where you need my help.

    --

    Regards,

    Vikram

  • Thank you for your reply Vikram,

    I assume that driver in PC may configure the MAC certain way and then MAC will issue some commands to PHY that will configure the PHY a wrong way. In case the MAC and PHY MDIO interface is disconnected, the MAC does not have a chance to re-configure PHY. 

    Would this be a plausible explanation?

    Juraj

  • Hi Jurag,

    I will go with you but I am not sure how MAC is behaving. I will close this thread now. Kindly let me know if any further assistance is required.

    --

    Regards,

    Vikram