Hi Barry,

I reviewed the schematic and did not find any problem with it.

Checked and ok

• VDD decoupling

• VDDA filtering (RF block inductor plus bypass caps)

• ENABLE

• GTX_CLK

• LOCKREFN

• LOOPEN

• PRBSEN

• RREF

• RX_CLK

• LOS

• TESTEN

• TX_EN, TX_ER

• Serial inputs and outputs -> AC coupling and input resistance termination

• Parallel data inputs and outputs

Regards,

Rodrigo Natal

HSSC Applications Engineer