Hi Team,
My customer wants to know what's the voltage level on CANH&CANL would be if it's under RL=open and in dominant mode condition?
Best regards,
Albert Lee.
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Hi Team,
My customer wants to know what's the voltage level on CANH&CANL would be if it's under RL=open and in dominant mode condition?
Best regards,
Albert Lee.
Hi Albert,
You could consider VCC to be a conservative upper limit on the steady-state dominant differential output voltage when there is no resistive loading. To get a better idea of the typical behavior, you could reference Figure 4 and 5 in the datasheet. These show that for 0 mA load current the CANH high level is typically about 3.25 V and the CANL low level is typically about 0.5 V, giving a differential magnitude of 2.75 V.
Max
Hi Max,
Then for the low level of CANL, I think the voltage under 0.5V (0 ~ 0.5V) for the condition RL=0 is reasonable, is it correct?
Winston
Thanks~
Hi Winston,
Yes, variation across silicon process and with temperature could cause CANL voltages below 0.5 V, although it would be unlikely to be as low as 0 V due to circuitry in low-side driver intended to block reverse current flow.
Regards,
Max