Hello,
We are using the TI lane repeater with input equalization and output de-emphasis part DS100BR111 in our application. Two lane repeaters are used to interface 10G Ethernet b/w on board FPGA & SFP+ module. We are configuring the lane repeater in SmBus slave mode and the registers are configured for 10G-KR mode. Link is established with one FPGA SmBus 1<==> Lane Repeater 1 <==> SFP+ 1 line (both TX & RX) with an external 10G optical to PCIe module connected in test PC. But for the second link FPGA SmBus 2 <==> Lane Repeater 2 <==> SFP+ 2 with same register configuration as in link 1, packet loss is observed in both TX & RX. TX is somewhat ok in link 2 as packet error is triggered in FPGA after some 10 to 15 minutes of data transaction. Whereas RX of link 2 is able to receive around 6000 packets and then packet loss is triggered.
TX connected via channel A & RX connected via channel B of lane repeater for both links. So channel A will TX across fiber & channel B will RX from fiber for both links.
The CH A EQ setting at 0x0F is set at 0000 0000 for link 1 & 2.
Similarly CH B EQ setting at 0x16 is set at 0000 0000 for link 1 & 2. When link 2 RX (CH B) didn't worked, EQ setting is increased step by step and the packet loss become worst. Lost the second packet itself when 0x01 is set at 0x16. When increased to 20dB link itself is not detecting.
De-emphasis is set at -3.5dB for link 1 & 2
CH A/B Idle Threshold is kept at minimum
CH B output to FPGA SERDES pin wss first set at 1300mV for both link 1 & link 2. Link 1 works without any issue. But link 2 is having packet loss issue. Tried reducing CH B output to FPGA Vpp to 1100mV.
Anyone who can suggest a work around for this, please support.
Regards
Hafiz
