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DS50PCI402: DS50PCI402

Part Number: DS50PCI402

Dear Technical Support Team,

I have been trying following issue.

e2e.ti.com/.../930604

I tried various settings, but there was no combination to solve link up issue. It is NG even in Bypass mode.

Therefore, when DS50PCI402 was removed and connected with a patch wire, the link up issue was improved.
Is it possible that problems will occur if the wiring length is short?
Currently, the wiring length is within 10 cm.

Best Regards,

ttd

  • Greetings,

    1). I reviewed the older E2E case you had noted related to the AC coupling cap. I am assuming the issue you noted here is still related to the AC coupling Cap location. Or the scenario you mentioned about AC coupling Cap still applies. Could you please confirm?

    2). You noted "the link up issue was improved". Does it mean there is still some cases where link up is not successful? Please confirm.

    3). In your application, what is the data pattern coding being used? 

    4). Link up issue: Is this PCIe or other standard? Any idea as to where in the link up is the cause of the failure to link up?

    It would be helpful to understand these questions so we can get a better understanding of the root cause.

    Regards,, Nasser 

  • Hi Nasser ,

    Thank you for your reply.

    >1). I reviewed the older E2E case you had noted related to the AC coupling cap. I am assuming the issue you noted here is still related to the >AC coupling Cap location. Or the scenario you mentioned about AC coupling Cap still applies. Could you please confirm?

    >2). You noted "the link up issue was improved". Does it mean there is still some cases where link up is not successful? Please confirm.

    ⇒I remove AC coupling cap of RX side, this means only AC coupling cap of TX side based on older E2E.

        However  link up is not successful sometimes.

    >3). In your application, what is the data pattern coding being used? 

    >4). Link up issue: Is this PCIe or other standard? Any idea as to where in the link up is the cause of the failure to link up?

    ⇒PCIe Gen2 , so 8B/10B encoding.

    Again, Is there specification of minimum length(trace) to use EQ of DS50PCI402?

    If the length(trace) is shorter than 8 inch(FR4), is it not effective for using EQ?

    Best Regards,

    ttd

  • Hi TTD,

    Thanks for clarifications.

    Some equalizers may have residual gain in order of 2-3dB even when the device is optioned for bypass mode. Given your insertion loss for the pcb material you have, you can determine this translates to how many inches of trace length. 

    Regards,, Nasser

  • Hi Nasser,

    >Some equalizers may have residual gain in order of 2-3dB even when the device is optioned for bypass mode.

    According to the datasheet, bypass mode shows 0dB. 

    Does DS50PCI402  residual gain in order of 2-3dB? If yes, is it cause link issue like eye close?

    I recognize that"Bypass mode" = "Pattern only (no device)"

    But is it not correct?
    It is necessary to find out the cause of link issue with Bypass mode and OK  case is  only removing device(no device).

    PS. this issue seems to cause between some different lot (some lot OK , some lot NG).

    Best Regards,

    ttd

  • Greetings,

    Agreed. With EQ0=EQ1= float there is 0dB gain at 1.25GHz and 2.5GHz. Based on your FPGA TX side, i am thinking there may be potential de-emphasis or pre-emphasis. Is this a possibility? Also, is it possible to lower VOD on the FPGA or ASIC TX side? Do you see any difference?

    Regards,, nasser