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DS110DF410EVM: Help with programming on board DS110DF410 for synchronous PRBS31 output at 10.5GHz from 656.25MHz

Part Number: DS110DF410EVM

Hi all,

I am programming the retimer device onbard the EVM through I2C with a MCU broken out from another device.

I can achieve comms with the IC successfully and performs reads and writes on the device.

For the inputs I am using 4x 656.25MHz CML terminated inputs from another evaluation card that I can are input on each of the SMA diff pairs. I can see from the evaluation card that the CDR is locking on each of these as the 2 green LEDs light up at each point/

I can also see an output which I suspect is at the desired frequency but I do not think that this is a PRBS pattern.

Could I ask for some assistance on whether the register writes I am making are correct for setting up a synchronous PRBS31 pattern output?

These register values are:

Ds10df410ProgramListEntry_t programTable[] = {
    {0x60, 0x90, 0xFF},  /* Setting value of PPM count. */
    {0x61, 0xB3, 0xFF},  /* Setting value of PPM count. */
    {0x62, 0x90, 0xFF},  /* Setting value of PPM count. */
    {0x63, 0xB3, 0xFF},  /* Setting value of PPM count. */
    {0x64, 0xFF, 0xFF},  /* Setting value of PPM tolerance. */
    {0x0C, 0x00, 0x08},  /* Turn Single Bit Limit Check Off */
    {0x09, 0x04, 0x04},  /* Enable divsel override */
    {0x18, 0x00, 0x70},  /* Select Divide by 1 */
    {0x30, 0x00, 0x0F},  /* Disable PRBS Gen */
    {0x1E, 0x00, 0xE0},  /* Select PRBS Gen */
    {0x09, 0x20, 0x20},  /* Enable Mux Override */
    {0x1E, 0x80, 0xE0},  /* Select PRBS Gen */
    {0x1E, 0x10, 0x10},  /* Powerup PRBS Gen Analog */
    {0x79, 0x20, 0x60},  /* Enable PRBS generator and disable PRBS checker */
    {0x30, 0x0B, 0x0F},  /* Powerup PRBS Clk and select PRBS31 */
};

Thanks for your time,

Sean.

  • Hi,

    The values for 0x60 thru 0x63 don't look correct. See below my recommended values for 10.5Gbps.

    • 0x60 = 0x80
    • 0x61 = 0xB4
    • 0x62 = 0x80
    • 0x63 = 0xB4

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • Hi rodrigo,

    I just realised I'd copied in my old register settings for 10.3125GHz clock PPM.

    Thanks for your reply, the values I had for the 10.5GHz where these values that you listed which now confirms that they are good thanks.

    I spent some time yesterday trying different register values with the SigCon GUI tool and I got a few register sets that achieve certain items but not one that feels like it fully 'works' yet.

    I should note that right now my register sets are targetting 10.3125 just as this was a test case, my finall aim is to update the PPM and my input clocks to be for 10.5GHz.

    1. My first register set can achieve CDR lock and output PRBS data but the PRBS data not the correct data rate.

    2. My other set of registers can achieve PRBS data at the correct data rate but the CDR does not lock.

    Register set 2 is probably the one that feels the closest to being correct but I can not sure why the CDR does not lock. 2 is a branch of 1 where I change ragister 0x18 to diide by 1 then 0x9 to load the DIV_SEL value.

    I've include both register sets. Please could you give me your thoughts on why register set 2 may not be CDR locking? (my setup is taking a 644.53125MHz clock into the channel and outputting 10.3125MHz and my PPM values are configured to achieve this, however I lose CDR lock when I set the DIV_SEL to be different, is this expected behaviour?)

    0x0    Channel 1_0x00    00
    0x1    Channel 1_0x01    00
    0x2    Channel 1_0x02    00
    0x3    Channel 1_0x03    41
    0x4    Channel 1_0x04    00
    0x5    Channel 1_0x05    00
    0x6    Channel 1_0x06    00
    0x7    Channel 1_0x07    00
    0x8    Channel 1_0x08    07
    0x9    Channel 1_0x09    EC
    0xA    Channel 1_0x0A    00
    0xB    Channel 1_0x0B    0F
    0xC    Channel 1_0x0C    08
    0xD    Channel 1_0x0D    20
    0xE    Channel 1_0x0E    93
    0xF    Channel 1_0x0F    69
    0x10    Channel 1_0x10    3A
    0x11    Channel 1_0x11    20
    0x12    Channel 1_0x12    A0
    0x13    Channel 1_0x13    30
    0x14    Channel 1_0x14    80
    0x15    Channel 1_0x15    10
    0x16    Channel 1_0x16    7A
    0x17    Channel 1_0x17    36
    0x18    Channel 1_0x18    00
    0x19    Channel 1_0x19    23
    0x1A    Channel 1_0x1A    00
    0x1B    Channel 1_0x1B    00
    0x1C    Channel 1_0x1C    24
    0x1D    Channel 1_0x1D    00
    0x1E    Channel 1_0x1E    99
    0x1F    Channel 1_0x1F    52
    0x20    Channel 1_0x20    00
    0x21    Channel 1_0x21    00
    0x22    Channel 1_0x22    00
    0x23    Channel 1_0x23    40
    0x24    Channel 1_0x24    40
    0x25    Channel 1_0x25    00
    0x26    Channel 1_0x26    00
    0x27    Channel 1_0x27    00
    0x28    Channel 1_0x28    00
    0x29    Channel 1_0x29    00
    0x2A    Channel 1_0x2A    30
    0x2B    Channel 1_0x2B    00
    0x2C    Channel 1_0x2C    72
    0x2D    Channel 1_0x2D    80
    0x2E    Channel 1_0x2E    00
    0x2F    Channel 1_0x2F    06
    0x30    Channel 1_0x30    0A
    0x31    Channel 1_0x31    20
    0x32    Channel 1_0x32    11
    0x33    Channel 1_0x33    88
    0x34    Channel 1_0x34    BF
    0x35    Channel 1_0x35    1F
    0x36    Channel 1_0x36    31
    0x37    Channel 1_0x37    0A
    0x38    Channel 1_0x38    00
    0x39    Channel 1_0x39    00
    0x3A    Channel 1_0x3A    A5
    0x3B    Channel 1_0x3B    00
    0x3C    Channel 1_0x3C    00
    0x3D    Channel 1_0x3D    00
    0x3E    Channel 1_0x3E    80
    0x3F    Channel 1_0x3F    00
    0x40    Channel 1_0x40    00
    0x41    Channel 1_0x41    01
    0x42    Channel 1_0x42    04
    0x43    Channel 1_0x43    10
    0x44    Channel 1_0x44    40
    0x45    Channel 1_0x45    08
    0x46    Channel 1_0x46    02
    0x47    Channel 1_0x47    80
    0x48    Channel 1_0x48    03
    0x49    Channel 1_0x49    0C
    0x4A    Channel 1_0x4A    30
    0x4B    Channel 1_0x4B    41
    0x4C    Channel 1_0x4C    50
    0x4D    Channel 1_0x4D    C0
    0x4E    Channel 1_0x4E    60
    0x4F    Channel 1_0x4F    90
    0x50    Channel 1_0x50    88
    0x51    Channel 1_0x51    82
    0x52    Channel 1_0x52    A0
    0x53    Channel 1_0x53    46
    0x54    Channel 1_0x54    52
    0x55    Channel 1_0x55    8C
    0x56    Channel 1_0x56    B0
    0x57    Channel 1_0x57    C8
    0x58    Channel 1_0x58    57
    0x59    Channel 1_0x59    5D
    0x5A    Channel 1_0x5A    69
    0x5B    Channel 1_0x5B    75
    0x5C    Channel 1_0x5C    D5
    0x5D    Channel 1_0x5D    99
    0x5E    Channel 1_0x5E    96
    0x5F    Channel 1_0x5F    A5
    0x60    Channel 1_0x60    00
    0x61    Channel 1_0x61    00
    0x62    Channel 1_0x62    00
    0x63    Channel 1_0x63    00
    0x64    Channel 1_0x64    00
    0x65    Channel 1_0x65    00
    0x66    Channel 1_0x66    00
    0x67    Channel 1_0x67    20
    0x68    Channel 1_0x68    00
    0x69    Channel 1_0x69    0A
    0x6A    Channel 1_0x6A    44
    0x6B    Channel 1_0x6B    00
    0x6C    Channel 1_0x6C    00
    0x6D    Channel 1_0x6D    00
    0x6E    Channel 1_0x6E    00
    0x6F    Channel 1_0x6F    00
    0x70    Channel 1_0x70    03
    0x71    Channel 1_0x71    20
    0x72    Channel 1_0x72    00
    0x73    Channel 1_0x73    00
    0x74    Channel 1_0x74    00
    0x75    Channel 1_0x75    00

    Best regards,

    Sean.

  • Hi, couple additional suggestions below.

    1. Below is the PRBS generator enable routine from our programming guide. Could you double check your current write routine relative to this one?
    2. Try disabling ppm check by setting channel register 0x2F[2]=0, to see if it helps

    Table 35. Register Writes to Enable PRBS Generator

     

    STEP

    SHARED/CHANNEL REGISTER SET

    OPERATION

    REGISTER ADDRESS [HEX]

    REGISTER VALUE [HEX]

    WRITE MASK [HEX]

    COMMENT

    1

    Channel

    Write

    09

    20

    20

    Override Output Multiplexer

    Select.

    2

    Channel

    Write

    1E

    80

    E0

    Turn on serializer (ser_en=1).

    3

    Channel

    Write

    1E

    10

    10

    Power-up PRBS Generator.

    4

    Channel

    Write

    30

    00

    08

    Reset PRBS Clock.

    5

    Channel

    Write

    30

    08

    08

    Power-up PRBS Clock.

    6

    Channel

    Write

    30

    00

    02

    03

    Select PRBS9 pattern. Select PRBS31 pattern.

    7

    Channel

    Write

    0D

    20

    20

    Enable PRBS Clock triggering on Div/Clock so that the eye diagram is viewable. Disabling results in Pattern Cycle triggering.