TSB82AA2B: minimize jitter

How large is the jitter? This sounds as if the 8 kHz output does not indicate when the timer rolls over, but when the cycle start packet is actually sent. The cycle start packet contains the current timer value to allow receivers on the bus to compensate for this delay, but with the plain GPIO signal, this compensation is not possible.

Bit 21 handles cycle master duties. To prevent becoming root, you have to set the root-holdoff bit (bit 0 in register 1 of the PHY).

Clemens Ladisch said:

Bit 21 handles cycle master duties. To prevent becoming root, you have to set the root-holdoff bit (bit 0 in register 1 of the PHY).

Hi Guru, I am using the DP83848 PHY. Is there a similar root-holdoff register in that PHY, or is just clearing bit 21 in the TSB82AA2B link controller enough to prevent the node from becoming the root? 

Thanks

Hi,

The DP83848 is an Ethernet PHY, do you have the right part number?

Thanks

David

Which chip is connected to the TSB82AA2B's PHY_xxx pins?

Whoops, sorry David. 

I meant the TSB41BA3 1394 PHY. Copying and pasting can be dangerous. 

However the root-holdoff description for the TSB41BA3 says that bit tells the PHY to become the root... 

I want to NOT be the root. 

I was thinking if I CLEARED bit 21 of the Link control register of the TSB82AA2B link controller, that would prevent that node form being the cycle master and thus prevent that node from becoming the root node.