Hi TI,
I've been testing the DS110DF410 on my test card. This is 12 DS110DF410 transmitting 48 channels of PRBS31 data at 10.5 GHz. These channels are being output onto short tracks to an optical transciever and received by an FPGA on a destination device.
All channels on all DS110DF410 are being programmed through I2C from a MCU device and R/W registers can be read back to confirm that the values are correct. These register settings are supplied below.
Programming occurs as a register dump boradcast to all channels on the device.
I had confirmed the register settings on the DS110DF410EVM using the SigCon Architect GUI tool.
I have determined that my endpoint device is not the problem by lane swapping at the output connector that connects to the retimer I can get all lanes on the destination device to work but half of the outputs on my test card from the DS110DF410 are not (all lanes connected to TX0 and TX1 of retimer devices).
The output from two channels on each device that go to TX0 and TX1 are locking to the signal but showing a saturated BER of 1.55E-2.
The output from the two other channels lock and run error free.
This is the case for all 12 DS110DF410 devices and having reviewed the schematic and layout the P and N are correct directions and the routing method is very similar between all channels and the fact that TX2 and TX3 run perfectly and are configured in the same way makes me think there might be something going wrong when the device is programmed.
The registers that are being programmed to all devices on all channels is given below:
Ds110df410ProgramListEntry_t ds110df410ProgramTable[] = {
{0x00, 0x00, 0xFF},
{0x01, 0x00, 0xFF},
{0x02, 0xD8, 0xFF}, // from DC
{0x03, 0xA5, 0xFF},
{0x04, 0x00, 0xFF},
{0x05, 0x00, 0xFF},
{0x06, 0x00, 0xFF},
{0x07, 0x00, 0xFF},
{0x08, 0x00, 0xFF},
{0x09, 0x20, 0xFF},
{0x0A, 0x10, 0xFF},
{0x0B, 0x0F, 0xFF},
{0x0C, 0x00, 0xFF}, // from 0x08
{0x0D, 0x20, 0xFF},
{0x0E, 0x93, 0xFF},
{0x0F, 0x69, 0xFF},
{0x10, 0x3A, 0xFF},
{0x11, 0x20, 0xFF},
{0x12, 0xA0, 0xFF},
{0x13, 0x30, 0xFF},
{0x14, 0x00, 0xFF},
{0x15, 0x10, 0xFF}, // was 0x10, then 0x53,
{0x16, 0x7A, 0xFF},
{0x17, 0x36, 0xFF},
{0x18, 0x40, 0xFF},
{0x19, 0x23, 0xFF},
{0x1A, 0x00, 0xFF},
{0x1B, 0x03, 0xFF},
{0x1C, 0x24, 0xFF},
{0x1D, 0x00, 0xFF},
{0x1E, 0x99, 0xFF},
{0x1F, 0x55, 0xFF},
{0x20, 0x00, 0xFF},
{0x21, 0x00, 0xFF},
{0x22, 0x00, 0xFF},
{0x23, 0x40, 0xFF},
{0x24, 0x00, 0xFF},
{0x25, 0x00, 0xFF},
{0x26, 0x00, 0xFF},
{0x27, 0x3C, 0xFF}, // was 0x3E
{0x28, 0x93, 0xFF}, // was 0x9C
{0x29, 0x40, 0xFF},
{0x2A, 0x30, 0xFF},
{0x2B, 0x00, 0xFF},
{0x2C, 0x72, 0xFF},
{0x2D, 0x80, 0xFF},
{0x2E, 0x00, 0xFF},
{0x2F, 0x06, 0xFF},
{0x30, 0x0A, 0xFF},
{0x31, 0x20, 0xFF},
{0x32, 0x11, 0xFF},
{0x33, 0x88, 0xFF},
{0x34, 0xBF, 0xFF},
{0x35, 0x1F, 0xFF},
{0x36, 0x31, 0xFF},
{0x37, 0x1f, 0xFF}, // was 0x00
{0x38, 0x00, 0xFF},
{0x39, 0x00, 0xFF},
{0x3A, 0xA5, 0xFF},
{0x3B, 0x00, 0xFF},
{0x3C, 0x00, 0xFF},
{0x3D, 0x00, 0xFF},
{0x3E, 0x80, 0xFF},
{0x3F, 0x00, 0xFF},
{0x40, 0x00, 0xFF},
{0x41, 0x01, 0xFF},
{0x42, 0x04, 0xFF},
{0x43, 0x10, 0xFF},
{0x44, 0x40, 0xFF},
{0x45, 0x08, 0xFF},
{0x46, 0x02, 0xFF},
{0x47, 0x80, 0xFF},
{0x48, 0x03, 0xFF},
{0x49, 0x0C, 0xFF},
{0x4A, 0x30, 0xFF},
{0x4B, 0x41, 0xFF},
{0x4C, 0x50, 0xFF},
{0x4D, 0xC0, 0xFF},
{0x4E, 0x60, 0xFF},
{0x4F, 0x90, 0xFF},
{0x50, 0x88, 0xFF},
{0x51, 0x82, 0xFF},
{0x52, 0xA0, 0xFF},
{0x53, 0x46, 0xFF},
{0x54, 0x52, 0xFF},
{0x55, 0x8C, 0xFF},
{0x56, 0xB0, 0xFF},
{0x57, 0xC8, 0xFF},
{0x58, 0x57, 0xFF},
{0x59, 0x5D, 0xFF},
{0x5A, 0x69, 0xFF},
{0x5B, 0x75, 0xFF},
{0x5C, 0xD5, 0xFF},
{0x5D, 0x99, 0xFF},
{0x5E, 0x96, 0xFF},
{0x5F, 0xA5, 0xFF},
{0x60, 0x80, 0xFF},
{0x61, 0xB4, 0xFF},
{0x62, 0x80, 0xFF},
{0x63, 0xB4, 0xFF},
{0x64, 0xFF, 0xFF},
{0x65, 0x00, 0xFF},
{0x66, 0x00, 0xFF},
{0x67, 0x20, 0xFF},
{0x68, 0x00, 0xFF},
{0x69, 0x0A, 0xFF},
{0x6A, 0x44, 0xFF},
{0x6B, 0x00, 0xFF},
{0x6C, 0x00, 0xFF},
{0x6D, 0x00, 0xFF},
{0x6E, 0x00, 0xFF},
{0x6F, 0x00, 0xFF},
{0x70, 0x03, 0xFF},
{0x71, 0x20, 0xFF},
{0x72, 0x00, 0xFF},
{0x73, 0x00, 0xFF},
{0x74, 0x00, 0xFF},
{0x18, 0x00, 0xFF},
{0x09, 0x24, 0xFF},
{0x1E, 0x10, 0x10}, /* Set Bit 4 */
{0x30, 0x00, 0x08}, /* Clear bit 3*/
{0x30, 0x08, 0x08}, /* Set bit 3*/
{0x0D, 0x20, 0x20}, /* Set bit 5 */
{0x09, 0x20, 0x20}, /* Set bit 5 */
{0x1E, 0x80, 0xE0}, /* Write 0x04 to bits 7:5 */
{0xFF, 0xFF, 0xFF},
};
We have confirmed that all values that can be written have taken and can be read back. Is there anyway that programming 4 channels in this way could result in 2 channels working and 2 channels not working?
Thanks,
Sean Suttie.
