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TPD12S521: Differential line trace impedance

Part Number: TPD12S521

Hello team,

According to the DS 11.2 layout example, the input and output patterns are connected at both side on the board via the IC.

In this case, I think it seems like the both PCB trance and IC's impedance should be considered.

Does it require any impedance adjustment considering IC's impedance?

Could you please let me know the recommended impedance adjustment procedure? (e.g. Impedance value, sub-layer GND, etc)

Also, I'd like to perform simulation after the impedance adjustment.

Could you please give me the S-parameter? I found IBIS model but didn't find S-parameter description.

On the other hand, the 2.3 Routing with VIAs explains one-sided connection. It focuses on explaining the effect of vias. However this device should be used with small VIA inductance and both-sided connection, correct?

Regards,

Itoh