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DP83TC811S-Q1: RGMII in DP83TC811s

Part Number: DP83TC811S-Q1
Other Parts Discussed in Thread: DP83867IS, , DP83TC811

Hi team,

I am writing to seek help for RGMII standard, especially the TX_CTRL.

In DP83TC811s datasheet, RGMII interface TX_CTRL true table is shown below. When data comes, TX_CTRL/RX_CTRL should change between 1 and 0. At the negative edge of TX_CLK, the TX_ER should be low.

 

But from DP83867is datasheet, when in RGMII is used for 1000M mode and no error, RX_CTRL should always high.

 

Below is the testing waveform, Blue is TX_CTRL and yellow is TX_Dx, it conflict with our datasheet, which causes the IP error.

Could you please analyze why RGMII in two datasheet are different? Is there something misunderstand?

Thanks a lot.

 

Best regards

Chen

  • Hi team,

    I am writing to seek help for RGMII standard, especially the TX_CTRL.

    In DP83TC811s datasheet, RGMII interface TX_CTRL true table is shown below. When data comes, TX_CTRL/RX_CTRL should change between 1 and 0. At the negative edge of TX_CLK, the TX_ER should be low.

     

    But from DP83867is datasheet, when in RGMII is used for 1000M mode and no error, RX_CTRL should always high.

     

    Below is the testing waveform, Blue is TX_CTRL and yellow is TX_Dx, it conflict with our datasheet, which causes the IP error.

    Could you please analyze why RGMII in two datasheet are different? Is there something misunderstand?

    Thanks a lot.

    Best regards

    Chen

  • Hello Chen,

    The DP83TC811S-Q1 is a 100Base-T1 PHY. The DP83867IS can operate at 1000Base-T, among others. As such, there is a 10x discrepancy in the data rate. This is alleviated through a 5x difference in RX/TX clock speeds (125MHz in 1G speed vs 25MHz is 10/100 speed) but also is accounted through Double Data Rate (DDR) in which data is also sampled on the falling edge of the clock during 1G speed only. This explains the discrepancy between the two datasheets.

    Since the speed shown here is of the DP83TC811, the rate is only 100Mbps, so during the falling edge of the clock, TX_CTRL should be '0' as the data rate is different than what you had shown in the DP83867 screenshot.

    Sincerely,

    Gerome

  • Hi Gerome,

    Thanks for your reply.

    Now we need to figure out TX_ER signal is active high or negative high in different situation, Audo Phy 100M RGMII, traditional Phy 100M RGMII and 1000M RGMII.

    So in my understanding, DP83TC811S also match RGMII standard, and just 100M RGMII is different from 1000M RGMII which causes this misunderstanding, am I right?

    Could you please also confirm if there is difference between auto Phy's 100M RGMII and traditional Phy's 100M RGMII interface?

    Thanks a lot.

    Best regards

    Chen

  • Hello Chen,

    You are correct in your understanding that the primary difference is between 1000M RGMII and 100M RGMII. There is no difference regarding the RGMII standard between automotive and traditional ethernet.

    Sincerely,

    Gerome

  • Hi Gerome,

    This information is very important. Now we are stuck at this point.

    Do you happen to have some material about 100M RGMII standard? I can only find 1000M standard online.

    Thanks a lot.

    Best regards

  • Please also see the description both in online documents and DP83867is datasheet as below. I am very confused about this message.

    Could you please give some solid information about TX_ER polarity? And do you know if there is registers can change TX_CTRL(TX_ER) polarity?

    Thanks a lot.

  • Hello Chen,

    The RGMII standard will act the same regardless of the MDI speed in terms of the signaling. However, the biggest difference is during 1000Mbps mode, during the falling edge you will have data present that is vital to the communication as this allows DDR. During 10 and 100Mbps operation, there may be data on the falling edge as well, but it will most likely be a duplicate, and as this is not DDR during these modes, it will not affect the communication.

    Regarding TX_ER, this is an output from the MAC so if there were controls for it, it would be there. However, as this is a standard that the PHY must follow to communicate, I do not expect there to be any way to change the polarity.

    Sincerely,

    Gerome

  • Hi Gerome,

    In my understanding, TX_CTRL control logic in auto phy standard 802.3bw is different from the one in 100M or 1000M RGMII interface, which conflict with the conclusion you mentioned before. Could you please give some more comments and details about this?

    I want to make myself more clear below.

    From DP83TC811s datasheet, during normal data transition, TX_CTRL on positive edge of CLK should be 1, TX_CTRL on negative edge should be 0.

    From DP83867IS datasheet, during normal data transition, however, TX_CTRL on positive edge and negative edge of CLK should be both 1.

    In below description, 100M logic is the same with 1000M logic.

    So in my understanding, TX_CTRL control logic in auto phy standard 802.3bw is different from the one in 100M or 1000M RGMII interface, am I right?

    Could it be possible there is more than one version of RGMII regulation?

    Appreciate if you can give some comments.

    Thanks.

    Best regards

  • Hello Chen,

    After talking with the team, this seems to be a discrepancy between our table and the one showed in the standard. The first and second columns of table 13 in our datasheet will be lining up with columns two and three of the table in the standard document. 

    So for clarification, TX_CTRL will be made high on the rising and falling edges of the clock when there is normal data transmission. This would be [1,1] on the standard table, which would have EN = 1 and ER = 0, which aligns with table 13 within our datasheet. This will be the same regardless of the speed of the MDI (10/100/1000) with the differences being whether or not DDR will be present or not (data present during the falling edge of clock may be duplicated in 10/100 mode) as well as the clock frequencies (2.5MHz for 10Mbps, 25MHz for 100Mbps, and 125MHz for 1Gbps). 

    Sincerely,

    Gerome

  • Hi Gerome,

    Thanks for the clarification.

    Thus DP83TC811S's RGMII logic is not 802.3bw standard neither, am I right?

    And we need to change the logic from standard to the one in DP83TC811s datasheet.

  • Hi Chen,

    That's correct. IEEE802.3bw dictates data communication on the MDI line over automotive ethernet at 100Mbps. This is independent of the RGMII standard as that is on the MII portion of the PHY.

    Sincerely,

    Gerome