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TUSB8043A: USB 3.x Signal Integrity, Eye Diagram, and Trace Impedance - How tricky is it?

Charles Gervasi
Expert 2270 points
Part Number: TUSB8043A

I am new to USB 3.0.  How much on-board matching an iterative changes to trace geometry are required?  Is it a case where if you conservatively follow the layout guidelines, you can pass on your first attempt?

I have worked with 5GHz RF traces and impedance matching with a VNA, but my experience with high-speed digital islimited to the 400Mbs range.  I don't have a feel for how sensitive 5 Gbps is to subtleties in layout.  Do people typically use special materials like Rogers with lower dielectric constants or can you use normal FR-4-like substrates?  

Do you typically need a scope fast enough to see the eye diagram at 5 Gbps? 

Fortunately, the interface on my board is 12Mbps USB.  The Hub chip would only be moving data.  It could be kept close to the connectors.  But at 5Gbps, one inch of trace is about one bit period, which feels staggeringly fast to me.  

  • +1
    TI__Guru 60865 points

    Hi Charles,

    It shouldn't  have to be iterative.  We can provide you with layout guidelines and the EVM layout as a starting point.  The key points are trace length matching, differential impedance matching, and avoiding discontinuities.  FR4 is fine, but I would recommend using 4 layers or more.  2 layer designs can be trickier to implement.

    Layout guidelines here:  https://www.ti.com/lit/an/slla414/slla414.pdf

    Let me know if you need the EVM layout as a reference.  TI can also help review your layout.

    The USB 3.0 eye diagram process is a bit more involved than USB 2.0.  You will need to load the XHCI HSETT tool from usb.org to force the ports in compliance mode and then you will need special test fixtures to access the signals and a function generator to force the ports to change compliance patterns.  What kind of scopes do you have available?  Usually the scope vendor has a USB 3.x compliance software program that makes the process easier.

    If the interface on your board is 12 Mbps, what is running at 5Gbps?  The USB 3.0 and USB 2.0 traffic are isolated from each on the bus and within the hub.  Can you share a block diagram?

    Regards,

    JMMN

  • 0 in reply to JMMN
    Expert 2270 points

    The layout guidelines look like what we've been doing since I read Dr. Howard Johnson's book 20 years ago, but now it's more than an order of magnitude faster.

    JMMN said:
    What kind of scopes do you have available? 

    I have a DSO9254A. 20Gsps is fast, but that's 4 samples per bit period.  Is that too slow?

    JMMN said:
    you will need special test fixtures to access the signals and a function generator to force the ports to change compliance patterns. 

    What are the test fixtures called?  I can find info on the XHCI HSETT tool, but I don't know what that hardware fixture is called.

    JMMN said:
    If the interface on your board is 12 Mbps, what is running at 5Gbps?  The USB 3.0 and USB 2.0 traffic are isolated from each on the bus and within the hub.  Can you share a block diagram?

    It's like this:

     

  • +1 in reply to Charles Gervasi
    TI__Guru 60865 points

    Hi Charles,

    It looks like Keysight has some videos and notes about taking USB 3.0 eyes with that series of scope, so it should be fast enough.  

    You can see the official test fixtures for USB compliance here:  https://www.usb.org/estore

    Regards,

    JMMN

  • 0 in reply to JMMN
    Expert 2270 points
    JMMN said:
    It looks like Keysight has some videos and notes about taking USB 3.0 eyes with that series of scope, so it should be fast enough. 

    My reading of the USB 3 validation info from Keysight, is we need a faster scope. Our DSO9254A is 2.5GHz.

    It makes intuitive sense that to take any measurements of a 5Gbps signal, whether just looking at the waveform or getting analyses like of jitter histogram, we need a scope faster than 2 * 5Gbps = 10Gbps.  

    Thanks for this info.  It's helpful to know people are making it work, even on two-layer FR4 boards.  

  • 0 in reply to Charles Gervasi
    TI__Guru 60865 points

    Ok, let us know if you need help with schematic or layout review.  We definitely don't recommend a 2 layer board though!

    Have a good weekend,

    JMMN