Other Parts Discussed in Thread: TCA9406, TCA9509, , TCA9800
Hello, I read some articles about how a rise-time accelerator can reduce power dissipation for 2-wire bus (e.g. I2C). However I couldn't find any real world performance numbers on how much energy is being saved by using a bus accelerator instead of e.g. 2.2 kOhm pull-up resistors (fast-mode). We are working on a wearable, which would have 4 devices on an I2C bus (work on 3.3V but some devices could also work on 1.8V if this was available), including a heart rate monitor and accelerometer, both of which will have ODR rate 100-400Hz. Thus we were looking into using a bus accelerator for energy reduction when reading the sensor data (since when the SDA/SCL is pulled LOW, the power is wasted 10kOhm (built-in accelerator pull-ups) / 2.2kOhm (pull-ups without accelerator) ~ 5 times). Do you have any calculations / tests showing how much energy would actually be saved using any of your accelerators? I noticed some of your provided options TCA9416, TCA9406, TCA9509 and it seems that TCA9416 is the latest/best one for energy constrained applications? We want to ensure lowest power consumption AND the PCB area possible, regardless of price, thus do you think rise-time accelerator would be a good fit for our scenario?
I would calculate these numbers myself, however the datasheet has quite many acronyms, thus makes it more difficult analysing it. Also I couldn't see but can I use a single side e.g. A with voltage VCCA=3.3V, while VCCB=0V, which would work as an accelerator ONLY (no voltage translation) and thus potentially less current would be drawn by the chip? What is the quiescent current (when voltage on SCL_A=VCCA and SDA_A=VCCA) and active current (when SDA_A/SCL_A are both pulled LOW)?
Thank you for taking the time to help us out!