[FAQ] TUSB1064: How do I debug DP Alt Mode over USB Type-C interface?

The most common problems with USB-C DisplayPort (DP) Alternate Mode stem from the fact that the video connection is usually stable with using legacy laptops and monitors and many engineers are not familiar with the order of events that occur in DisplayPort and the added steps when DP video data is transmitted over a USB Type-C cable.

To start the debugging process, it is recommended to have a protocol analyzer that can decode both the USB Type-C PD controller and DP Link Training protocol. If a protocol analyzer is not available, we can use oscilloscope, multi-meter, PD controller and USB Type-C SuperSpeed Crosspoint MUX pins/registers to debug any issues.  

Check the Hot Plug Detect (HPD) signal

For the TUSB546A-DCI, TUSB1046A-DCI, TUSB1146, TUSB564, and TUSB1064 USB Type-C SuperSpeed Crosspoint MUX, when HPDIN is LOW for greater than 2ms, all DisplayPort lanes are disabled while the AUX to SBU switch will remain closed.

Use a multi-meter to check both the source and the sink side to make sure HPD is driven high (3.3V).

On the source side, HPD is provided by the PD controller, though a “virtual” HPD, to the source and the TUSB546A-DCI, TUSB1046A-DCI, TUSB1146.

On the sink side, HPD is provided by the sink to the PD controller and the TUSB564 and the TUSB1064.

HPD serves two purposes:

1. HPD serves as sink presence and absence notification. When HPD is high or 3.3V, this indicates the presence of the sink. When HPD is low or 0V for greater than 2ms, this indicates the absence or the removal of the sink.
2. HPD serves as an interrupt from the sink to the source. When HPD is low or 0V between 0.5 to 1ms, this indicates an interrupt event, a sink request to the source to read the sink’s DPCD register.

Check the SBU/AUX MUX implementation

A SBU/AUX MUX is implemented to support USB Type-C normal and flip orientation. The MUX can be implemented as part of the PD controller, of the USB    Type-C SuperSpeed Crosspoint MUX, or a standalone MUX (ex. TS3USBCA4). For both the source and the sink side, it is important that the SBU/AUX MUX is only implemented once by the PD controller, the USB Type-C SuperSpeed Crosspoint MUX , OR the standalone MUX. 

Check SBU/AUX MUX common mode voltage:

The 2MΩ pull-down resistors on SBU1 and SBU2 are representative of the leakage of ESD and EMI/RFI components including termination to ensure no floating nodes, and are intended to show compliance with zSBUTermination in the USB Type-C specification.

For AUXp, it needs to be pulled down to GND with a 100k resistor on the source side, and pulled up to 3.3V with a 1M resistor on the sink side. This will result in a common mode voltage of ~0.3V when connected.

For AUXn, it needs to be pulled up to 3.3V with a 100k resistor on the source side, and pulled down to GND with a 1M resistor on the sink side. This will result in a ~3V common mode voltage when connected.

Using a multi-meter to check the common mode voltage of SBU1/2 and AUXp/n on both the source and the sink side, make sure the common mode voltage meets the PD controller or the MUX common mode voltage requirement. If the common mode voltage is not correct, then the DP Link Training will not pass through the MUX.

Check the SBU/AUX signal integrity

If the SBU/AUX common mode voltage is correct, then we need to probe the SBU/AUX bus to verify the signal integrity. The TUSB546A-DCI, TUSB1046A-DCI, TUSB1146, TUSB564, and TUSB1064 USB Type-C SuperSpeed crosspoint MUX snoops the SBU/AUX bus as part of the power management feature. When AUX snoop feature is enabled, the SYNCs defined by the DisplayPort standard must be received in order for AUX snoop feature to function properly. If the SYNCs is corrupted due to signal integrity, then it is best to disable AUX snoop.

DP Link Training

After all the above steps have been checked and there is still no display on the monitor, we will need to look at the DP link training to understand the root cause of the issue.

Once the EDID and DPCD have been read, the source starts the link training. The link training consists two phases: a clock recovery phase and a channel equalization phase. During these two phases, the sink reports the received signal quality and request the desired signal amplitude and pre-emphasis level. The source updates its PHY amplitude and pre-emphasis level base on the sink request.

The clock recovery phase is completed when the clock recovery flag is set and the link training moves onto the channel equalization phase. The channel equalization phase is completed when Channel Equalization, Symbol-Lock, Inter-lane Alignment flags are all set.

Pay attention to the data rate and lane configuration and make sure the source/sink are correctly communicating the data rate and lane configuration. It is importance that the source, the USB Type-C SuperSpeed crosspoint MUX, and the sink all have the same lane configuration. For example, if the source and sink are configured in a fixed 4 DP lane mode while the crosspoint MUX is configured in a 2 DP lane mode, then the link training will always fail on lane 2 and 3. Once the data rate and lane configuration are set correctly, take a look at the clock recovery and channel equalization training phase to see where the issue is. If clock recovery and channel equalization training phase fail at higher data rate or four lane configurations, try with lower data rate or one/two lane configurations.

Best Regards

David