DP83848 bit stream for compliance mode

Jason,

Most 100Base-TX tests are performed with scrambled idles.  The DP83848 will transmit scrambled idles by default when configured for 100Base-TX.  Therefore, the only required configuration is to set register 0x00 to 0x2100.

In case they should need additional test modes, test by test configuration details for 100M compliance are below.   Please let us know if you have any questions.

Patrick

---------------------------------------------------------------------------------------------------------------------------------------

A few notes on the test methodology and terminology:

1. In the terminology below, 1 T equals 1 bit time (8ns).
2. The DP83848 does not support causing a scrambled halt line state by asserting TX_ER.  TX_ER is used for support of repeaters and this device is not targeted at repeaters.  Per the IEEE 802.3 spec, using scrambled idles is permitted:

IEEE 802.3-2005

25.4.5 Change to 9.1.9,  "Jitter"

The jitter measurement specified in 9.1.9 of TP-PMD may be performed using scrambled IDLEs.

ANSI X3.263-1995: Annex J AOI Template, 9.1.6 Rise Time, 9.1.6 Fall Time, 9.1.6 Rise Fall Symmetry, 9.1.9 Transmit Jitter

Configure the device to use scrambled idles by forcing 100Base-T full duplex.  Write 0x2100 to register address 0x00.

ANSI X3.263-1995: 9.1.2.2 Differential Output Voltage, 9.1.4 Signal Amplitude Symmetry, 9.1.3 Waveform Overshoot

Enable a 14T/6T pattern that alternates between a positive 14T pulse and a negative 14T pulse with 6T between each positive and negative pulse.

To configure the 14T/6T pattern:

1. Force 100M (write 0x2100 to address 0x00)
2. Enable 14T/6T pattern (write 0x2407 to address 0x1F)
3. After testing, disable 14T/6T pattern (write 0x2400 to address 0x1F)

ANSI X3.263-1995: 9.1.8 Distortion (Duty Cycle)

Enable a 100M 2T pattern (+1, +1, 0, 0, -1, -1) for DCD testing. The ANSI TP-PMD tests specifies a pattern with 16ns widths, hence two bit times on the wire.

To configure the 2T pattern:

1. Force 100M (write 0x2100 to address 0x00)
2. Enable 2T pattern (write 0x2406 to address 0x1F)
3. After testing, disable 2T pattern (write 0x2400 to address 0x1F)

ANSI X3.263-1995: 9.1.5 Transmitter Return Loss, 9.1.5 Receiver Return Loss

For 100Base-T, configure the device to use scrambled idles by forcing 100Base-T full duplex.  Write 0x2100 to register address 0x00.

For 10Base-T, configure the device to use scrambled idles by forcing 10Base-T full duplex.  Write 0x0100 to register address 0x00.

----------------------------------------------------------------------------------------

Additional register sequences for 100Base-TX output signaling

----------------------------------------------------------------------------------------

To output a Pseudo-random packet in 100Mbps:

1. Force 100M, full duplex (write 0x2100 to address 0x00)
2. Force 100M good link (write 0x0120 to address 0x16)
3. Start BIST transmission of PSR9 pattern (write 0x1to bit 8 of address 0x19)