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60Mhz 120Mbit/s (data on both clock edges) LVDS board (FR4) to board signal conditioning question.

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Replies: 3

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Hi,
I am designing a LED video display board which uses three LVDS pairs for data distribution (clk + 2 data channels).
Clock rate is 60Mhz, with data on both edges. Using the two data channels the total data rate is 240Mbit/s.
From a data point of view, it is a multidrop bus, where each pcb sees the same data.

The LED panels are 340 mm wide (FR4 material), and data goes in on left side and goes out on the right side,
and will be "daisy chained" with up to 10 boards in row. This means the signals goes through 3.4 meters of FR4 pcb.
I will repeat the LVDS signals on each board.
I am worried about added clock jitter and skew so the margins will become smaller and smaller towards the
end of each LED panel row.

Is it a good or bad idea to have LVDS repeater/buffer on each pcb ? 

The options I have:
1. Using a quad LVDS buffer like DS15BR400TSQ on each pcb (adding very litter skew and jitter I Believe) and
then locally drop the signals on each pcb from the bus with a DS90LV032A (placed close to the outputs of the buffer).

2. Translate to single ended with LV032 and then "retransmit" with a LV031 towards next board?


3. Only buffer LVDS signals on, lets say, every 4:th pcb.


I suppose the speed is fairly low in LVDS terms, but adding jitter/skew from 10 pcb boards would reduce the margins.

Anyone with experience of a similar LVDS configuration ?
What could I expect from a configuration like this ?

Would be great if I could use higher data rates as well (100Mhz maybe).
What LVDS devices should I use.

Kind regards
T

 

3 Replies

  • Hi Tobias,

    Option numbers 1 and 3 are viable plans but option number two would not be a good choice. Usually a TTL (single ended) signal is translated to an LVDS/CML (differential signal) to be transported around not the other way around. Single ended signals are very susceptible to noise so converting these signals to differential signals provides a noise immunity as the same amount of noise is present on both the P and N portion of the signal. This is why I stated above that options 1 and 3 are viable choices in which the the differential signal is simply buffered along the way.

    Regards,

    Mike

    Regards,

    Michael Peffers

    Industrial Interface Applications

    Analog Wire: Get Connected

  • In reply to Michael Peffers:

    Thanks  Mike,

    Regarding option two, the idea was to have a trace of maybe a few cm single ended only (just to tap the signal to a LVC244 buffer). But, I understand
    that doing this conversion back and forth on each pcb (when up to ten in rows) will add a lot of extra skew.

    So chosing between buffer on each board or only on every 4th.
    What would you recomend ?
    (I suppose an LVDS input on each pcb, four between each buffer then, will load the LVDS line to much?).

    Will I be able to run 60Mhz or more on 10 PCBs in serie (340mm each segmetn, 3.4meters in total) ?
    (I mean there is no reclocking done, so the jitter/skew will add for each panel).

    What buffer would you suggest?

    Kind regards
    Tobias

  • In reply to Tobias P:

    Tobias,

    My major concern would be the jitter accumulation in this scheme.   As you note, each hop will add to the jitter and skew, so there will be a limit to the number of hops that you can make before the signal will not be able to be recovered.   I would either add reclocking to remove jitter and skew, or consider a different architecture - possibly one with a star configuration and dedicated links to each of the display elements.

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