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Connection between two separate MACs and the dual port PHY DP83849IVS

Vasanthan Nagarajan
Intellectual 260 points

We are going to use DP83849IVS in our design which is a dual-port PHY chip.

 

It is having one MDC/MDIO pairs for both the PHYs inside the chip.

 

In our design, we have two MACs which will be trying to access the PHY chips through the common MDC/MDIO pairs.

 

Can you please tell us whether we can go for the below configuration inside the FPGA to connect to the common MDC/MDIO pairs. FYI, in the EVK, the jumper setting is provided in such a way that either PortA/PortB can access the MDC/MDIO pairs at any point of time and not both can access the management pairs simultaneously.

 

Based on any previous implementation, please let us know how we can connect two MACs’ Management pairs to the common Management pairs of PHY chip so that the MACs can access the corresponding PHYs.

  • 0
    TI__Mastermind 31600 points

    I do not believe I have seen a previous implementation like this.  How would control of the MDC/MDIO be managed?  That is to say, how would you prevent MAC_1 and MAC_2 from both driving the signals at the same time?

    Also, MDIO is a bi-directional I/O.  How would input from the PHY to the FPGA be handled on MDIO reads?

    Patrick

  • 0 in reply to Patrick OFarrell
    Intellectual 260 points
    But in the Beckoff's EtherCAT soft ip datasheet, it is mentioned in the list of supported PHYs.
  • 0 in reply to Vasanthan Nagarajan
    TI__Mastermind 23675 points

    Hi Vasanthan,

    Our PHYs comply with the IEEE 802.3 standard. If you look at how the serial management interface works (MDIO/MDC) you will see that only one device can be the master. The master will provide the clock (MDC). The master and slaves have control of the MDIO. As long as you can confirm that only one master will be acting as a master at a time, then I see no issue in the above implementation. You will just need to make sure only one MAC is controlling the MDC at a time.

    Regards,

    Ross