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TPD4E004: Clamp Voltage

Ryuuichi machida
Guru 11525 points
Part Number: TPD4E004

Hi,

I want you to confirm whether this device can clamp "Vcc+Vf" at any conditon or not.

According to datasheet of TPD4E004, there is following description in section 8.2.2. 

5. The V CC pin can be connected in two different ways:
(a) If the V CC pin is connected to the system power supply, the TPD4E004 works as a transient suppressor
for any signal swing above V CC + V F . A 0.1-μF capacitor on the device V CC pin is recommended for ESD
bypass.

I understood when user connect "Vcc" pin to power supply, clamp voltage will be "Vcc+Vf" at any condition (Ex IEC 61000-4-2 +8kV contact).

Could you please confirm whether my understanding is correct or not ?

If my understanding is not correct, could you please tell me whether there is ESD protection device which can clamp fixed voltage at any condtion or not ?

Best Regards,

Machida

  • 0
    TI__Expert 3500 points
    Machida-

    Your understanding is correct. If you place a voltage on the Vcc pin, it will set the clamping voltage on the IO pins to VCC + Vf. For example, if you only expect your signal to go to a maximum of 3.3V, placing Vcc at 4V will clamp the voltage on the signal lines below 5V. If you expect 5V on your signal line however, you don't need to put a voltage on the VCC pin, which will set your clamping to closer to 7V. This flexibility allows you to use the same device in multiple designs.

    Does that answer your question? I believe you have the correct understanding!

    Thanks,
    Alec
  • 0 in reply to Alec Forbes
    Guru 11525 points
    Hi Alec-san,

    Thank you for your reply.
    I have one question for your answer.
    >For example, if you only expect your signal to go to a maximum of 3.3V, placing Vcc at 4V will clamp the voltage on the signal lines below 5V.
    I was understanding if we expect our signal to go to a maximum of 3.3V, then we should place Vcc at 2.5V , and then the signal line is clamped 3.3V((Vclamp(3.3V) = Vcc + Vf).
    However, according to your explanation, I recognized that we should place Vcc at "expected maximum voltage + Vf (4V = 3.3V + Vf)".
    Could you please give me comment about my understanding ?

    Thanks in advance,
    Machida
  • 0 in reply to Ryuuichi machida
    TI__Expert 3500 points

    Machida-

    Because the TPD4E004 is a diode, there will be some leakage as you approach the clamping voltage and the diode starts to turn on. Therefore, if you have a signal at 3.3V and put your clamping voltage at 3.3V you will see a lot of leakage current during typical operation. We generally recommend putting your working voltage a about a volt higher than your working voltage as it will ensure that your signal is not effected. It will have a little bit higher clamping voltage as you have predicted, but the clamping voltage increase is minimal and a necessary consequence of not harming your signal.

    In your example then, I would recommend placing VCC at between 3.5V to 4V, any lower could cause issues with signal integrity that would ruin your application.

    Does that make sense? Please feel free to ask any follow up questions if it is still not clear!

    Thanks,

    Alec

  • 0 in reply to Alec Forbes
    Guru 11525 points

    Hi Alec-san,

    I understood why you described Vcc=4V for my example.

    Thank you for your explanation.

    BR,

    Machida