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DS110DF1610: CDR could not LOCK

Jeff Chen71
Expert 1345 points
Part Number: DS110DF1610

Hi,

     Customer facing DS110DF1610 could not lock ISSUE. We are test three signal frequency as below,only the 9.95328Ghz can be locked,the other two can not and both reg 0x27 and 0x28 were 0. 

   10.709225 // not lock

    9.95328  //  lock (even set reg 0x2f or 0x60~0x63 both setting can lock)

    2.48832 //  not lock 

We had try to set reg0x64 to 0xff and reg0x2f[2] to 0 to turn off PPM check but it's no effect.  

 

register log(10.709225G):

   0x60    0x8B

   0X61   0XB5

   0X62   0X8B

   0X63   0XB5

   0X64   0X64

   0X67   0X20

   0X2F   0X26

   0X09   0X04

   0X18   0X00

   0X36    0X30

   0X0C   0X00

   0X27   0X00

   0X28   0X00

after set reg0x36 from 0x30 to 0x00 ( Disable Fast_lock all cap dac ref clock enabled) the CDR was locked.(10.709225G)

   0x36   0x00

   0x27   0X1D

   0X28  0X5A

register log(9.95328G):

  0X27 0X1D

  0X28 0x5E

  0x36 0x30

Thanks

  • 0
    TI__Mastermind 19135 points

    Hi. See my recommendations below.

    CDR rate settings for 10.709225Gbps

    0x60 = 0x8C

    0x61 = 0xB5

    0x62 = 0x8C

    0x63 = 0xB5

    0x64 = 0xFF

     

    9.95328Gbps -> No problem with this rate

     

    CDR rate settings for 2.48832Gbps

    Use same settings for 0x60 thru 0x64 as used for 9.95328Gbps

    Set divider ratio to 4 via channel register 0x18 (see register description below)

    Disable SBT check by setting 0x0C[3]=0

    18

    7

    0

    RW

    N

    RESERVED

    6

    1

    RW

    Y

    PDIQ_SEL_DIV2

    These bits will force the divider setting if 0x09[2] is set.

    000: Divide by 1

    001: Divide by 2

    010: Divide by 4

    011: Divide by 8

    100: Divide by 16

    All other values are reserved.

    5

    0

    RW

    Y

    PDIQ_SEL_DIV1

    4

    0

    RW

    Y

    PDIQ_SEL_DIV0

    3

    0

    RW

    N

    RESERVED

    2

    0

    RW

    N

    DRV_PD_R_EN

    1: Enables the shut down termination resistor to be present when the driver is powered down with channel register 0x15[3]

    0: Normal operation, resistor is disconnected from output for propper driver operation

    1:0

    0

    RW

    N

    RESERVED

    Cordially,

    Rodrigo Natal HSSC Applications Engineer

     

  • 0 in reply to Rodrigo Natal
    Expert 1345 points

    Hi Rodrigo ,

         Following your suggestion,and disable PPM_CHECK / FLD_CHECK via channel register 0x2F . The frequency 2.48832Ghz and 1.24416Ghz can be locked now. But 10.709225G could not .

    Q1: Is it ok to disable PPM_CHECK/FLC_CHECK?

         After change EQ_EN_MR_MODE from MID_RATE to FULL_RATE, the 10.709225G can be locked.  But it have a problem,when we unplug optical fiber from channel RX_0A side the channel_0A change to unlock status we think it's right ,but channel_0B still locked. 

    Q2: Is it ok to change EQ_EN_MR_MODE from MID_RATE to FULL_RATE and why it can improve CDR lock?

    Q3: Why channel_0B hold locked when unplug input fiber?

    Q4: Know customer didn't enable DFE, because the datasheet do not description to much about the parameter. Do you have document talk about that?  

    Thanks

  • 0 in reply to Jeff Chen71
    TI__Mastermind 19135 points

    Hi,

     

    Disabling FLD check is fine. I would suggest re-enabling PPM check and seeing whether setting 0x64 = 0xFF allows the channel to lock for these lower data rates

     

    For 10.7G I would recommend to use full rate mode.

     

    I’m not sure why the retimer channel would show CDR locked after unplugging fiber. MY hypothesis would be that the optical module electrical output still has some output signal chatter present with no cable inserted.

     

    For this 10.7G link case I would make the following suggestions to see if they help the link perform more robustly.

     

    • I would recommend to make sure that FIR post-cursor weight is set to 0 on channel TX_0A; this is done by setting channel register 0x3F[5:0]=0

    • I would recommend to force CTLE = 0x00 on the channel in question. I also link DFE might help. See below channel register operations.

     

    REG

    Value

    Comment

    0x31

    0x40

    Set Adapt mode 2

    0x2D

    0x88

    Enable EQ override

    0x03

    0x00

    Set EQ = 00

    0x3A

    0x1E

    0x00

    0xE1

    Set EQ = 00

    Enable the DFE

    0x0A

    0x1C

    Puts the CDR into RESET

    0x0A

    0x10

    Releases the CDR from reset

     

  • 0 in reply to Rodrigo Natal
    Expert 1345 points

    Hi Rodirgo,

         Following your parameter, channel 0A could be locked at 10.709225Ghz. But the loop back channel can't be locked. Customer had try to bypass loop back channel 0B ,and direct connect channel 0A to their test equipment

    the the communication is ok. Now we still debug on it, if we have  question I will create a new thread. 

    Thanks.