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DS90UB913A-Q1: Needed time for DIGITAL RESET0/1

Part Number: DS90UB913A-Q1

Hi all,

I would like to know the needed time for DIGITAL RESET0 and 1. For each reset, how many clocks does this device need to be reset? Or how much time is reasonable waiting time for processor? Of course the processor shall watch LOCK/PASS pins at deserializer but the customer needs to estimate the initialization period for reset.

Regards,
RYO

  • Hello RYO,

    what time are you looking for exactly? You said for digital reset, but from what till what exactly?!

  • Hi Hamzeh,

    PLL by PCLK needs time of 22ms (tDDLT) + 2ms (tPLD) at 913A-914A in each datasheet. I need the time from issuing DIGITAL RESET1 to re-PLL by PCLK. How long does it take for DIGITAL RESET1. Of course, the delay dependent on its design such as one of FPD-Link signal lane and PCLK detection can be dismissed here. In this case, would this time be much smaller than 1ms or would it affect 10ms-order?

    Regards,
    RYO

  • RYO,

     let me rephrase it and please correct me if I am wrong.

     You are looking for the Re-Lock time after Digital reset, correct? i.e. the time the Deserializer requires to re-Lock to the PCLK after issuing a digital rest??!

  • Hi Hamzeh 

    I am working with RYO for the same project and let me answer for your confirmation:

    What we are asking is NOT "Re-LOCK time after Digital reset" but the "the time how long it takes to complete Digital reset transaction".

    Because we understood from data sheet that PLL and Re-Lock requires about 24ms so

    What is missing to understand the "total time duration from trigger Digital reset to Re-LOCK state " is

    "the time how long it takes to complete Digital reset transaction".

    We understood that above time is not defined as spec so we just ask reference info out side of the spec. or TI's recommendation. and simple answer is OK.

    Thanks and Regards

    Shosei Hatsuyama

  • Hello Shosei,

    Digital reset it self requires les than 1ms.