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DS90UB960-Q1: DS90UB960-Q1, frame sync error, stream time out

Jin-Suk Choi
Intellectual 1650 points
Part Number: DS90UB960-Q1

Hi~ Team.

Customer using DS90UB953 *4EA + DS90UB960 application and happen frame sync error(stream time out) as below. Would you please advise how to resolve?

[ 2008.433460]
just4kox csi_fmts [0].code = 0x00002011
[ 2008.439532]
just4kox csi_fmts [1].code = 0x0000200f
[ 2008.490898]
just4kox csi_fmts [0].code = 0x00002011
[ 2008.496998]
just4kox csi_fmts [1].code = 0x0000200f
[ 2008.516108]
just4kox csi_fmts [0].code = 0x00002011
[ 2008.522177]
just4kox csi_fmts [1].code = 0x0000200f
[ 2008.540948]
just4kox csi_fmts [0].code = 0x00002011
[ 2008.547072] just4kox csi_fmts [1].code = 0x0000200f
[ 2008.583662] ti960 3
0030: TI960 in broadcast mode
[ 2008.839175] intel
ipu4 isys intel ipu4 isys0: csi2 4 received fatal error
[ 2008.846770] intel
ipu4 isys intel ipu4 isys0: csi2 4 error: FIFO overflow
[ 2008.854353] intel
ipu4 isys intel ipu4 isys0: csi2 4 error: DPHY non recoverable synchronization error
[ 2030.851497] intel
ipu4 isys intel ipu4 isys0: stream stop time out
[ 2030.858465] intel
ipu4 isys intel ipu4 isys0: s_stream TI964 4 0030 ( ext
[ 2032.898496] intel
ipu4 isys intel ipu4 isys0: stream close time out
[ 2032.905579] intel
ipu4 isys intel ipu4 isys0: Intel IPU4 CSI 2 4 capture 0: cleaning active queue 4
[ 2032.905586] intel
ipu4 isys intel ipu4 isys0: Intel IPU4 CSI 2 4 capture 0: cleaning active queue 3
[ 2032.905593] intel
ipu4 isys intel ipu4 isys0: Intel IPU4 CSI 2 4 capture 0: cleaning active queue 2
[ 2032.905599] intel
ipu4 isys intel ipu4 isys0: Intel IPU4 CSI 2 4 capture 0: cleaning active queue 1
[ 2032.917431] intel
ipu4 isys intel ipu4 isys0: s_stream TI964 4 0030 ( ext
[ 2034.945512] intel
ipu4 isys intel ipu4 isys0: stream stop time out
[ 2034.952475] intel
ipu4 isys intel ipu4 isys0: s_stream TI964 4 0030 ( ext
[ 2036.992494] intel
ipu4 isys intel ipu4 isys0: stream close time out
[ 2036.999669] intel
ipu4 isys intel ipu4 isys0: Intel IPU4 CSI 2 4 capture 2: cleaning active queue 3
[ 2036.999676] intel
ipu4 isys intel ipu4 isys0: Intel IPU4 CSI 2 4 capture 2: cleaning active queue 2
[ 2036.999682] intel
ipu4 isys intel ipu4 isys0: Intel IPU4 CSI 2 4 capture 2: cleaning active queue 1
[ 2036.999688] intel
ipu4 isys intel ipu4 isys0: Intel IPU4 CSI 2 4 capture 2: cleaning active queue 0
[ 2039.039391] intel
ipu4 isys intel ipu4 isys0: stream stop time out
[ 2039.046392] intel
ipu4 isys intel ipu4 isys0: s_stream TI964 4 0030 ( ext
[ 2041.150351] intel
ipu4 isys intel ipu4 isys0: stream close time out
[ 2041.157440] intel
ipu4 isys intel ipu4 isys0: Intel IPU4 CSI 2 4 capture 3: cleaning active queue 4
[ 2041.157447] intel
ipu4 isys intel ipu4 isys0: Intel IPU4 CSI 2 4 capture 3: cleaning active queue 3
[ 2041.157454] intel
ipu4 isys intel ipu4 isys0: Intel IPU4 CSI 2 4 capture 3: cleaning active queue 2
[ 2041.157459] intel
ipu4 isys intel ipu4 isys0: Intel IPU4 CSI 2 4 capture 3: cleaning active queue 1

Below is DS90UB960 register.

{0x32, 0x01},
0x01},/* Select CSI port 0
{0x4c, 0x01},
/* Select RX port 0
{0x58, 0x5D},
{0x5c, 0xe8},
{0x6d, 0x7C},
0x7C},/* FPD3_MODE (1100 --> DS90UB953 Q1) */
{0xD5, 0xF0},
{0x7c, 0x01},
/* Use RAW10 8bit mode
{0x70, 0x2B},
/* YUV422_8
{0x71, 0x2C},
{0x72, 0xE4},
{0xd2, 0x84},
{0x4c, 0x12}, /* Select RX port 1 */
{0x58, 0x5D},
{0x5c, 0xe8},
{0x6d, 0x7C},
{0xD5, 0xF0},
{0x7c, 0x01}, /* Use RAW10 8bit mode */
{0x70, 0x2B}, /* YUV422_8 */
{0x71, 0x2C},
{0x72, 0x39},
{0xd2, 0x84},
{0x4c, 0x24}, /* Select RX port 2*/
{0x58, 0x5D},
{0x5c, 0xe8},
{0x6d, 0x7C},
{0xD5, 0xF0},
{0x7c, 0x01}, /* Use RAW10 8bit mode */
{0x70, 0x2B}, /* YUV422_8 */
{0x71, 0x2C},
{0x72, 0x4e},
{0xd2, 0x84},

{0x4c, 0x38}, /* Select RX port3 */
{0x58, 0x5D},
{0x5c, 0xe8},
{0x6d, 0x7C},
{0xD5, 0xF0},
{0x7c, 0x01}, /* Use RAW10 8bit mode */
{0x70, 0x2B}, /* YUV422_8 */
{0x71, 0x2C},
{0x72, 0x93},
{0xd2, 0x84},
{0xB9, 0x18},
{0x42, 0x71},
//{0x10, 0x59},
{0x10, 0x91},
{0x19, 0x0A},
{0x1A, 0xD7},
{0x1B, 0x61},
{0x1C, 0xA0},
{0x18, 0x01},
{0x21, 0x01},
{0x20, 0x00},

  • 0
    TI__Intellectual 1025 points

    Hi Jin_suk,

    Based on the FIFO overflow, this looks like a potential bandwidth error. Can you send me the resolution, data type, and fps for each sensor? Aggregate bandwidth availability is 6.4 Gbps per CSI-2 TX port. If you are only using one port, this requires an average of 1.6 Gbps bandwidth per sensor or less.

    Regards,

    Carrie

  • 0 in reply to Carrie Kemmet
    TI__Intellectual 1650 points

    Hi~ Carrie.

    Please, refer below information and let me have your feedback.

    1.     Resolution : 1280 X 720

    2.     Data Type : YUV422

    3.     FPS : 30FPS

    Thanks.

  • 0 in reply to Jin-Suk Choi
    TI__Intellectual 1025 points

    Hello Jin-Suk,

    There are a few more parameters I would need to know to calculate exact bandwidth: YUV422 8 or 10 bit, vertical blanking, and the data rate.

    Assuming a vertical blanking of 10%, a data rate of 6.4 Gbps, and YUV 8 bit mode, your output bandwidth is 1.12 Gbps and your input bandwidth is 4*486.6 Mbps or 1.9 Gpbs. Because your input bandwidth exceeds your output bandwidth, the buffers are overflowing and most likely the source of your error.

    Regards,

    Carrie

  • 0 in reply to Carrie Kemmet
    Prodigy 40 points

    Hello, I'm software engineer for this project.

    This issue happend Intermittent.

    Mostly, It worked fine.

    When power on the board, some camera did not work.

    And, bandwidth of SoC has enough.

    This SoC is possible processing for FHD.

    So, I think that bandwidth is no problem.

    Regards,

  • 0 in reply to Carrie Kemmet
    Prodigy 40 points

    Hello, I'm software engineer for this project.

    This issue happend Intermittent.
    When power on the board, some camera did not working randomly.
    And, bandwidth of SoC is enough.
    This SoC is possible processing for FHD.

    So, I think that bandwidth is not cause of this issue.

    Regards,

    Carrie Kemmet said:

    Hello Jin-Suk,

    There are a few more parameters I would need to know to calculate exact bandwidth: YUV422 8 or 10 bit, vertical blanking, and the data rate.

    Assuming a vertical blanking of 10%, a data rate of 6.4 Gbps, and YUV 8 bit mode, your output bandwidth is 1.12 Gbps and your input bandwidth is 4*486.6 Mbps or 1.9 Gpbs. Because your input bandwidth exceeds your output bandwidth, the buffers are overflowing and most likely the source of your error.

    Regards,

    Carrie

    Carrie Kemmet said:

    Hello Jin-Suk,

    There are a few more parameters I would need to know to calculate exact bandwidth: YUV422 8 or 10 bit, vertical blanking, and the data rate.

    Assuming a vertical blanking of 10%, a data rate of 6.4 Gbps, and YUV 8 bit mode, your output bandwidth is 1.12 Gbps and your input bandwidth is 4*486.6 Mbps or 1.9 Gpbs. Because your input bandwidth exceeds your output bandwidth, the buffers are overflowing and most likely the source of your error.

    Regards,

    Carrie

  • 0 in reply to Hyounjin Moon
    TI__Intellectual 1025 points

    Hello Hyounjin,

    The total bandwidth from the four sensors at the input on the 960 has to be less than the aggregate bandwidth leaving the 960. The buffers will overflow otherwise. Even if the SoC has enough bandwidth, the problem can be caused by bandwidth availability on the deserializer.

    What is your number of lanes and your lane speed settings (found in CSI_CTL and CSI_PLL_CTL registers, respectively)?

    I calculated the input bandwidth to the 960 by multiplying (horiz_px * vert_px * frame_rate * bits_per_pixel). This came out to a bandwidth of 488 Mbps per sensor, so 1.95 Gbps total. If your CSI-2 output bandwidth is less than that, then the buffers inside the 960 can overflow. See section 7.4.20 for equations used to calculate output bandwidth. The example in 7.4.20.1 can be used to help guide the calculations, because you also have 4 identical sensors.

    Regards,

    Carrie

  • 0 in reply to Carrie Kemmet
    Prodigy 40 points

    Hello, Carrie

    What you mean is TI960 is not enough to use for four channel HD camera?

    I heard that this chip support HD camera.
    I wonder about, it is right.

    Additionally, The below is value of CSI_CTL, CSI_PLL_CTL registers on board.
    CSI_CTL : 0x01
    CSI_PLL_CTL : 0x02

    Regards,

  • 0 in reply to Hyounjin Moon
    TI__Intellectual 1025 points

    Hello Hyounjin,

    The 960 supports four full HD 1080p/2MP resolution at 60-Hz with 2 CSI ports. It can support four full HD 1080p/2MP resolution at 30-Hz if you are using 1 CSI port. It allows flexibility in programming the output lane configurations in the case of slower or faster input data rates.

    The configuration of your registers will affect how much output bandwidth the 960 can support, which could go down to 1 lane at 400 Mbps. To clarify, the 960 has an output bandwidth range per port of 400 Mbps to 6.4 Gbps depending on register configuration.

    Your register configuration allows for up to 3.2Gbps output bandwidth so that should be enough. I am currently working on your issue and will get back to you with more suggestions by tomorrow.

    Thank you,

    Carrie

  • 0 in reply to Carrie Kemmet
    TI__Intellectual 1025 points

    Good morning,

    Because you are using RAW10 mode, the VC-ID for each port is read from register 0x70. Try placing different values in the register for each RX port. For each value in register 0x70, make sure to preserve the first 6 bits (0x2B) which is a standard value for RAW10 data type.

    {0x4C, 0x01}  // RX port 0

    {0x70, 0x2B}  // VC-ID 0 | RAW10 DT

    {0x4C, 0x12}  // RX port 2

    {0x70, 0x6B}  // VC-ID 1 | RAW10 DT

    {0x4C, 0x24}  // RX port 2

    {0x70, 0xAB}  // VC-ID 2 | RAW10 DT

    {0x4C, 0x38}  // RX port 3

    {0x70, 0xEB}  // VC-ID 3 | RAW10 DT

    Additionally, ensure that the CSI_PLL_CTL register has the correct tx speed configuration for your receiver’s expected CSI data rate. Also, make sure that you have the correct number of lanes configured in CSI_CTL.

    If you still have issues, please send me a complete register dump for the 960 and I can look more closely at your configuration.

    Regards,

    Carrie

  • 0 in reply to Carrie Kemmet
    Prodigy 40 points

    Hello, Carrie

    I tested after apply to your advise.
    The result was almost same with previous.

    So, I hope to you that check my register value.

    The below is reading register value.
    The rest register have default value.

    Regards,


    ==================================
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x01
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x02
    0x1e
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x03
    0x40
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x04
    0xd0
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x05
    0x01
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x06
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x07
    0xfe
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x08
    0x1c
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x09
    0x10
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x0a
    0x7a
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x0b
    0x7a
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x0c
    0x0f
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x0d
    0x09
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x0e
    0x1d
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x0f
    0xff
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x10
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x11
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x12
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x13
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x14
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x15
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x16
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x17
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x18
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x19
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x1a
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x1b
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x1c
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x1d
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x1e
    0x04
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x1f
    0x02
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x20
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x21
    0x01
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x22
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x23
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x24
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x25
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x26
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x27
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x28
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x29
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x2a
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x2b
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x2c
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x2d
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x2e
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x2f
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x30
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x31
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x32
    0x01
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x33
    0x01
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x34
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x35
    0x01
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x36
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x37
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x38
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x39
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x3a
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x3b
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x3c
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x3d
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x3e
    0x00
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x3f
    0x00


    gr-mrb-64:~# i2cset -f -y 3 0x30 0x4C 0x01
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x58
    0x5d
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x5C
    0xe8
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x6D
    0x7c
    gr-mrb-64:~# i2cget -f -y 3 0x30 0xD5
    0xf0
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x7C
    0xc0
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x70
    0x2b
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x71
    0x2c
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x72
    0xe4


    gr-mrb-64:~# i2cset -f -y 3 0x30 0x4C 0x12
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x58
    0x5d
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x5C
    0xe8
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x6D
    0x7c
    gr-mrb-64:~# i2cget -f -y 3 0x30 0xD5
    0xf0
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x7C
    0xc0
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x70
    0x6b
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x71
    0x2c
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x72
    0x39


    gr-mrb-64:~# i2cset -f -y 3 0x30 0x4C 0x24
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x58
    0x5d
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x5C
    0xe8
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x6D
    0x7c
    gr-mrb-64:~# i2cget -f -y 3 0x30 0xD5
    0xf0
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x7C
    0xc0
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x70
    0xab
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x71
    0x2c
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x72
    0x4e


    gr-mrb-64:~# i2cset -f -y 3 0x30 0x4C 0x38
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x58
    0x5d
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x5C
    0xe8
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x6D
    0x7c
    gr-mrb-64:~# i2cget -f -y 3 0x30 0xD5
    0xf0
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x7C
    0xc0
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x70
    0xeb
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x71
    0x2c
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x72
    0x93
    gr-mrb-64:~# i2cget -f -y 3 0x30 0xB9
    0x33
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x42
    0x71
    gr-mrb-64:~# i2cget -f -y 3 0x30 0x10
    0x00

  • 0 in reply to Hyounjin Moon
    TI__Intellectual 1025 points

    Hello,

    In general, your register configuration looks fine. Make sure not to program any reserved registers. Try to leave the slave aliases in port specific register 0x5C as their defaults. In other words, do not change the slave alias for each port. They should all be different values.

    If this does not produce results, we can begin to use on-chip tools such as interrupts and maybe the pattern generation feature to separately verify and debug various aspects of the layout.

    Regards,

    Carrie