TDP158: About DDC bus signal

1. The TDP158 uses clock stretching for DDC transactions. Clock stretching is the ability to hold down the clock if it needs to reduce the bus speed. If you need the clock to be the same frequency but only translating the voltage between 3.3V and 5V, then you would need an external I2C level shifter.

2. The delay is between SCL_SRC and SCL_SNK, and SDA_SRC and SDA_SNK, not between SCL and SDA.

Thanks
David 

Hi David

Thank you for your quickly reply.

1. I understood. I introduce !2C level shifter for customer.

2. Sorry, I misunderstood. 28us delay between  SCL_SRC and SCL_SNK is device characteristic?

best regards

teritama

Teritama-san

For propagation delay, please refer to section 6.12, Figure 15, and Figure 16. The 28us delay is the device plus the PCB propagation delay.

Thanks

David

Hi David

Thank you reply.

Which is dominant by device or PCB in propagation delay?

And how much do you expect DDC propagation delay by this device?

best regards

teritama

Teritama-san

The delay should be dominated by the PCB. Please refer to section 6.12 for the DP158 propagation delay. 

If the DDC is going through the external I2C buffer, then you should refer to the I2C buffer propagation delay.

Thanks

David 

Hi David

>The delay should be dominated by the PCB.

⇒Thank you. I understood.

>Please refer to section 6.12 for the DP158 propagation delay. 

⇒Sorry, I can't find tPHL and tPLH in table.

   Please, teach me how I guess propagation delay. 

best regards

teritama