DS90UB949-Q1: display splash sometime in 949/940

Betty Guo

Part Number: DS90UB949-Q1

Hi team,

In 949/940 application, we found the display will splash sometimes in the end car oem. the LOCK and PASS status of 940 are high. if the LOCK goes to low, will reset 940.

there two 949 boards, A-SER of 949 is single output. only OUT0 have signal and OUT1 not. B-SER is dual mode, OUT1 &OU2 are the same. we suspect the 949 LVDS peformance is not good, which result in the 940 de-ser issue.

I attached customer eye diagram in A-SER board and B-SER board. could you help to check if it good for 940? and, in 940 side, how to change the setting to help solve splash issue, in 949 side, how to improve?

thanks.Serializer A-949.zip Serializer B-949.zip

over 3 years ago

0 Hamzeh Jaradat over 3 years ago

TI__Guru* 90250 points

Hello Betty,

what does "splash issue" means? Can you post a picture from the display?

0 Betty Guo over 3 years ago in reply to Hamzeh Jaradat

TI__Expert 7300 points

Hi Hamzeh,

display picture as below:

0 Betty Guo over 3 years ago in reply to Hamzeh Jaradat

TI__Expert 7300 points

in additional, for 940 side, customer only set reg 0x6B CSICFG1 to 0x50, for YUV422-8, please help check it ASAP.

many thanks,

0 Hamzeh Jaradat over 3 years ago in reply to Betty Guo

TI__Guru* 90250 points

Hello Betty,

it looks like you are using dual lane transmission but just displaying one lane on the display!

Can you check your Dual/Single lane configurations on both devices?

0 Betty Guo over 3 years ago in reply to Hamzeh Jaradat

TI__Expert 7300 points

Hi Hamzeh,

since 949 is designed by another company, my customer design 940. for 940, they only set the reg 0x6B CSICFG1 to 0x50, for YUV422-8, for others are by default.

so, the 940 is work in single, right?

one more question, this splash issue is only occur sometime, not always. if the 940 is in single mode, I think it should be splash always instead of occasiobnally. right?

0 Hamzeh Jaradat over 3 years ago in reply to Betty Guo

TI__Guru* 90250 points

Hello Betty,

No. Having default values means the device in Auto detect mode.

Can you ask them to force dual by changing reg 0x34[3] = 1 ?

Also can you tell me what is the used PCLK?

Additionally, can you please provide register dump in a good case and in the splash case?

0 Betty Guo over 3 years ago in reply to Hamzeh Jaradat

TI__Expert 7300 points

Hi Hamzeh,

PCLK is 30.78M

below is good case dump reg value, for the splash reg, it very hard to repeat,only inside the car. we haven't get it. can you help to anlysis base on current information? thanks,

i2c reg-940 good.log

# 
# ./rw_i2c.sh  
slave = 0x2c reg = 0x0 val = 0x58
slave = 0x2c reg = 0x1 val = 0x4
slave = 0x2c reg = 0x2 val = 0x0
slave = 0x2c reg = 0x3 val = 0xfffffff0
slave = 0x2c reg = 0x4 val = 0xfffffffe
slave = 0x2c reg = 0x5 val = 0x1e
slave = 0x2c reg = 0x6 val = 0x0
slave = 0x2c reg = 0x7 val = 0x1c
slave = 0x2c reg = 0x8 val = 0x0
slave = 0x2c reg = 0x9 val = 0x0
slave = 0x2c reg = 0xa val = 0x0
slave = 0x2c reg = 0xb val = 0x0
slave = 0x2c reg = 0xc val = 0x0
slave = 0x2c reg = 0xd val = 0x0
slave = 0x2c reg = 0xe val = 0x0
slave = 0x2c reg = 0xf val = 0x0
slave = 0x2c reg = 0x10 val = 0x0
slave = 0x2c reg = 0x11 val = 0x0
slave = 0x2c reg = 0x12 val = 0x0
slave = 0x2c reg = 0x13 val = 0x0
slave = 0x2c reg = 0x14 val = 0x0
slave = 0x2c reg = 0x15 val = 0x0
slave = 0x2c reg = 0x16 val = 0x0
slave = 0x2c reg = 0x17 val = 0x0
slave = 0x2c reg = 0x18 val = 0x0
slave = 0x2c reg = 0x19 val = 0x1
slave = 0x2c reg = 0x1a val = 0x0
slave = 0x2c reg = 0x1b val = 0x0
slave = 0x2c reg = 0x1c val = 0x2b
slave = 0x2c reg = 0x1d val = 0x40
slave = 0x2c reg = 0x1e val = 0x0
slave = 0x2c reg = 0x1f val = 0x0
slave = 0x2c reg = 0x20 val = 0x0
slave = 0x2c reg = 0x21 val = 0x0
slave = 0x2c reg = 0x22 val = 0x40
slave = 0x2c reg = 0x23 val = 0x20
slave = 0x2c reg = 0x24 val = 0x8
slave = 0x2c reg = 0x25 val = 0x0
slave = 0x2c reg = 0x26 val = 0xffffff83
slave = 0x2c reg = 0x27 val = 0xffffff84
slave = 0x2c reg = 0x28 val = 0x1
slave = 0x2c reg = 0x29 val = 0x0
slave = 0x2c reg = 0x2a val = 0x0
slave = 0x2c reg = 0x2b val = 0x0
slave = 0x2c reg = 0x2c val = 0x0
slave = 0x2c reg = 0x2d val = 0x0
slave = 0x2c reg = 0x2e val = 0x0
slave = 0x2c reg = 0x2f val = 0x0
slave = 0x2c reg = 0x30 val = 0x0
slave = 0x2c reg = 0x31 val = 0x0
slave = 0x2c reg = 0x32 val = 0xffffff90
slave = 0x2c reg = 0x33 val = 0x25
slave = 0x2c reg = 0x34 val = 0x1
slave = 0x2c reg = 0x35 val = 0x0
slave = 0x2c reg = 0x36 val = 0x0
slave = 0x2c reg = 0x37 val = 0xffffff8a
slave = 0x2c reg = 0x38 val = 0x0
slave = 0x2c reg = 0x39 val = 0x0
slave = 0x2c reg = 0x3a val = 0x0
slave = 0x2c reg = 0x3b val = 0x3
slave = 0x2c reg = 0x3c val = 0x20
slave = 0x2c reg = 0x3d val = 0xffffffe0
slave = 0x2c reg = 0x3e val = 0x23
slave = 0x2c reg = 0x3f val = 0x0
slave = 0x2c reg = 0x40 val = 0x43
slave = 0x2c reg = 0x41 val = 0x3
slave = 0x2c reg = 0x42 val = 0x3
slave = 0x2c reg = 0x43 val = 0x0
slave = 0x2c reg = 0x44 val = 0x60
slave = 0x2c reg = 0x45 val = 0xffffff88
slave = 0x2c reg = 0x46 val = 0x0
slave = 0x2c reg = 0x47 val = 0x0
slave = 0x2c reg = 0x48 val = 0xf
slave = 0x2c reg = 0x49 val = 0x0
slave = 0x2c reg = 0x4a val = 0x0
slave = 0x2c reg = 0x4b val = 0x8
slave = 0x2c reg = 0x4c val = 0x0
slave = 0x2c reg = 0x4d val = 0x0
slave = 0x2c reg = 0x4e val = 0x63
slave = 0x2c reg = 0x4f val = 0x0
slave = 0x2c reg = 0x50 val = 0x3
slave = 0x2c reg = 0x51 val = 0x10
slave = 0x2c reg = 0x52 val = 0x0
slave = 0x2c reg = 0x53 val = 0x1
slave = 0x2c reg = 0x54 val = 0xffffff80
slave = 0x2c reg = 0x55 val = 0x0
slave = 0x2c reg = 0x56 val = 0x0
slave = 0x2c reg = 0x57 val = 0x0
slave = 0x2c reg = 0x58 val = 0x0
slave = 0x2c reg = 0x59 val = 0x3f
slave = 0x2c reg = 0x5a val = 0x20
slave = 0x2c reg = 0x5b val = 0x20
slave = 0x2c reg = 0x5c val = 0x0
slave = 0x2c reg = 0x5d val = 0x0
slave = 0x2c reg = 0x5e val = 0x0
slave = 0x2c reg = 0x5f val = 0x0
slave = 0x2c reg = 0x60 val = 0x0
slave = 0x2c reg = 0x61 val = 0x0
slave = 0x2c reg = 0x62 val = 0x0
slave = 0x2c reg = 0x63 val = 0x0
slave = 0x2c reg = 0x64 val = 0x10
slave = 0x2c reg = 0x65 val = 0x0
slave = 0x2c reg = 0x66 val = 0x0
slave = 0x2c reg = 0x67 val = 0x0
slave = 0x2c reg = 0x68 val = 0x0
slave = 0x2c reg = 0x69 val = 0x0
slave = 0x2c reg = 0x6a val = 0x0
slave = 0x2c reg = 0x6b val = 0x50
slave = 0x2c reg = 0x6c val = 0xf
slave = 0x2c reg = 0x6d val = 0x42
slave = 0x2c reg = 0x6e val = 0x0
slave = 0x2c reg = 0x6f val = 0x0
slave = 0x2c reg = 0x70 val = 0x0
slave = 0x2c reg = 0x71 val = 0x0
slave = 0x2c reg = 0x72 val = 0x0
slave = 0x2c reg = 0x73 val = 0x7
slave = 0x2c reg = 0x74 val = 0x7
slave = 0x2c reg = 0x75 val = 0x8
slave = 0x2c reg = 0x76 val = 0x0
slave = 0x2c reg = 0x77 val = 0x0
slave = 0x2c reg = 0x78 val = 0x0
slave = 0x2c reg = 0x79 val = 0x0
slave = 0x2c reg = 0x7a val = 0x0
slave = 0x2c reg = 0x7b val = 0x4d
slave = 0x2c reg = 0x7c val = 0x2
slave = 0x2c reg = 0x7d val = 0x0
slave = 0x2c reg = 0x7e val = 0x0
slave = 0x2c reg = 0x7f val = 0x0
slave = 0x2c reg = 0x80 val = 0x0
slave = 0x2c reg = 0x81 val = 0x0
slave = 0x2c reg = 0x82 val = 0x0
slave = 0x2c reg = 0x83 val = 0x0
slave = 0x2c reg = 0x84 val = 0x0
slave = 0x2c reg = 0x85 val = 0x0
slave = 0x2c reg = 0x86 val = 0x0
slave = 0x2c reg = 0x87 val = 0x0
slave = 0x2c reg = 0x88 val = 0x0
slave = 0x2c reg = 0x89 val = 0x0
slave = 0x2c reg = 0x8a val = 0x0
slave = 0x2c reg = 0x8b val = 0x0
slave = 0x2c reg = 0x8c val = 0x0
slave = 0x2c reg = 0x8d val = 0x0
slave = 0x2c reg = 0x8e val = 0x0
slave = 0x2c reg = 0x8f val = 0x0
slave = 0x2c reg = 0x90 val = 0x0
slave = 0x2c reg = 0x91 val = 0x0
slave = 0x2c reg = 0x92 val = 0x0
slave = 0x2c reg = 0x93 val = 0x0
slave = 0x2c reg = 0x94 val = 0x0
slave = 0x2c reg = 0x95 val = 0x0
slave = 0x2c reg = 0x96 val = 0x0
slave = 0x2c reg = 0x97 val = 0x0
slave = 0x2c reg = 0x98 val = 0x0
slave = 0x2c reg = 0x99 val = 0x0
slave = 0x2c reg = 0x9a val = 0x0
slave = 0x2c reg = 0x9b val = 0x0
slave = 0x2c reg = 0x9c val = 0x0
slave = 0x2c reg = 0x9d val = 0x0
slave = 0x2c reg = 0x9e val = 0x0
slave = 0x2c reg = 0x9f val = 0x0
slave = 0x2c reg = 0xa0 val = 0x0
slave = 0x2c reg = 0xa1 val = 0x0
slave = 0x2c reg = 0xa2 val = 0x7d
slave = 0x2c reg = 0xa3 val = 0x0
slave = 0x2c reg = 0xa4 val = 0x0
slave = 0x2c reg = 0xa5 val = 0x0
slave = 0x2c reg = 0xa6 val = 0x0
slave = 0x2c reg = 0xa7 val = 0x0
slave = 0x2c reg = 0xa8 val = 0x0
slave = 0x2c reg = 0xa9 val = 0x0
slave = 0x2c reg = 0xaa val = 0x0
slave = 0x2c reg = 0xab val = 0x0
slave = 0x2c reg = 0xac val = 0x0
slave = 0x2c reg = 0xad val = 0x0
slave = 0x2c reg = 0xae val = 0x0
slave = 0x2c reg = 0xaf val = 0x0
slave = 0x2c reg = 0xb0 val = 0x0
slave = 0x2c reg = 0xb1 val = 0x0
slave = 0x2c reg = 0xb2 val = 0x0
slave = 0x2c reg = 0xb3 val = 0x0
slave = 0x2c reg = 0xb4 val = 0x0
slave = 0x2c reg = 0xb5 val = 0x0
slave = 0x2c reg = 0xb6 val = 0x0
slave = 0x2c reg = 0xb7 val = 0x0
slave = 0x2c reg = 0xb8 val = 0x0
slave = 0x2c reg = 0xb9 val = 0x0
slave = 0x2c reg = 0xba val = 0x0
slave = 0x2c reg = 0xbb val = 0x0
slave = 0x2c reg = 0xbc val = 0x0
slave = 0x2c reg = 0xbd val = 0x0
slave = 0x2c reg = 0xbe val = 0x0
slave = 0x2c reg = 0xbf val = 0x0
slave = 0x2c reg = 0xc0 val = 0x0
slave = 0x2c reg = 0xc1 val = 0x0
slave = 0x2c reg = 0xc2 val = 0x0
slave = 0x2c reg = 0xc3 val = 0x0
slave = 0x2c reg = 0xc4 val = 0x0
slave = 0x2c reg = 0xc5 val = 0x0
slave = 0x2c reg = 0xc6 val = 0x0
slave = 0x2c reg = 0xc7 val = 0x0
slave = 0x2c reg = 0xc8 val = 0xffffffc0
slave = 0x2c reg = 0xc9 val = 0x0
slave = 0x2c reg = 0xca val = 0x0
slave = 0x2c reg = 0xcb val = 0x0
slave = 0x2c reg = 0xcc val = 0x0
slave = 0x2c reg = 0xcd val = 0x0
slave = 0x2c reg = 0xce val = 0x0
slave = 0x2c reg = 0xcf val = 0x0
slave = 0x2c reg = 0xd0 val = 0x0
slave = 0x2c reg = 0xd1 val = 0x0
slave = 0x2c reg = 0xd2 val = 0x0
slave = 0x2c reg = 0xd3 val = 0x0
slave = 0x2c reg = 0xd4 val = 0x0
slave = 0x2c reg = 0xd5 val = 0x0
slave = 0x2c reg = 0xd6 val = 0x0
slave = 0x2c reg = 0xd7 val = 0x0
slave = 0x2c reg = 0xd8 val = 0x0
slave = 0x2c reg = 0xd9 val = 0x0
slave = 0x2c reg = 0xda val = 0x0
slave = 0x2c reg = 0xdb val = 0x0
slave = 0x2c reg = 0xdc val = 0x0
slave = 0x2c reg = 0xdd val = 0x0
slave = 0x2c reg = 0xde val = 0x0
slave = 0x2c reg = 0xdf val = 0x0
slave = 0x2c reg = 0xe0 val = 0x0
slave = 0x2c reg = 0xe1 val = 0x0
slave = 0x2c reg = 0xe2 val = 0x0
slave = 0x2c reg = 0xe3 val = 0x0
slave = 0x2c reg = 0xe4 val = 0x0
slave = 0x2c reg = 0xe5 val = 0x0
slave = 0x2c reg = 0xe6 val = 0x0
slave = 0x2c reg = 0xe7 val = 0x0
slave = 0x2c reg = 0xe8 val = 0x0
slave = 0x2c reg = 0xe9 val = 0x0
slave = 0x2c reg = 0xea val = 0x0
slave = 0x2c reg = 0xeb val = 0x0
slave = 0x2c reg = 0xec val = 0x0
slave = 0x2c reg = 0xed val = 0x0
slave = 0x2c reg = 0xee val = 0x0
slave = 0x2c reg = 0xef val = 0x0
slave = 0x2c reg = 0xf0 val = 0x5f
slave = 0x2c reg = 0xf1 val = 0x55
slave = 0x2c reg = 0xf2 val = 0x42
slave = 0x2c reg = 0xf3 val = 0x39
slave = 0x2c reg = 0xf4 val = 0x34
slave = 0x2c reg = 0xf5 val = 0x30
slave = 0x2c reg = 0xf6 val = 0x0
slave = 0x2c reg = 0xf7 val = 0x0
slave = 0x2c reg = 0xf8 val = 0x0
slave = 0x2c reg = 0xf9 val = 0x0
slave = 0x2c reg = 0xfa val = 0x0
slave = 0x2c reg = 0xfb val = 0x0
slave = 0x2c reg = 0xfc val = 0x0
slave = 0x2c reg = 0xfd val = 0x0
slave = 0x2c reg = 0xfe val = 0x0

0 Hamzeh Jaradat over 3 years ago in reply to Betty Guo

TI__Guru* 90250 points

Hello Betty,

for this PCLK they do not need dual Mode. Single lane is more than enough!

I can check the register values in the good mode, but I believe this is not sufficient since all values would be "okay" !

0 Betty Guo over 3 years ago in reply to Hamzeh Jaradat

TI__Expert 7300 points

Hi Hamzeh,

thanks reply, can you give the more clear solution hwo to solve this issue and response below items:

1. before I attached eyediagram, how about the eyediagram performance? does is good for De-ser.

2. as you mentioned before, they using dual lane transmission but just displaying one lane on the display, customer need force dual by changing reg 0x34[3] = 1, right?

3. for PCLK, hwo to configure the PCLK? increase or decrease, I'm confused about this.

0 Hamzeh Jaradat over 3 years ago in reply to Betty Guo

TI__Guru* 90250 points

Hello Betty,

here are my comments to your questions:

1) I can see Eye-Diagram for 949A and 949B. What are these and what is the different between them?

Also what is meant by Dash-board Power ON or power OFF?

I do not see any measurements on DES!!

2) They do not need Dual. As I said, PCLK is just 30MHz.

3) WHat do you mean by configuring PCLK? where and why?

PCLK is coming from the data source connected at the input of SER. We can't configure/change it on our devices.

0 Betty Guo over 3 years ago in reply to Hamzeh Jaradat

TI__Expert 7300 points

Hi Hamzeh,

1）I have said in my fisrt question I submit. they measure the eye-disgram on Deser

2) you mean customer only need single-lane transmission can solve splash issue? but befor, you told me that let they force dual by changing reg 0x34[3] = 1. which one is correct?

based on question 2), if 949 in dual-lane, 948 in single-lane, what happens to the display.

thank you

0 Hamzeh Jaradat over 3 years ago in reply to Betty Guo

TI__Guru* 90250 points

1) I do not see any Eye-diagram measurement from the DES !!! I see only Eye-diagrams from SER.

Also what is meant by Dash-board Power ON or power OFF?

I can see the Eye-diagrams with Dash-board Power ON are very bad. But other Eye-diagram are good.

2) As I said, again, due to the low PCLK, they do not need Dual lanes. They need to use either single lane or automatic mode.

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DS90UB949-Q1: display splash sometime in 949/940