Part Number: DP83867E
I have a question about DP83867E.
Is the input to the XIN a crystal unit? Is it a crystal oscillator or external oscillator?
Also, the input specs of XIN are the DC specs of the oscillator, so please tell me the specs when using a crystal.Please tell me the driving power when using a crystal oscillator.
You can connect crystal between XI and XO pin as mentioned in datasheet. The other option is to connect external oscillator. The specs you share are for external oscillator. Crystal requirements are also there in datasheet, but we recommend to use 50ohms ESR crystal and with total variation of less than 100ppm.
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In reply to Vikram Sharma99:
Vikram sanThank you so much for your cooperation always!We have several additional questions.<Question1>In case of 3.3V and 2.5V clock source, DC blocking caps require.So, XI has internal bias voltage, right?(Is XI Pierce oscillator?)<Question2>In relation to <Question1>, if XI is Pierce oscillator, it seems that R55 of DP83867EVM is unnecessary.(Pleas refer to following circuit.)Because there is bias resistance internally.Is our recognition correct?<Question3>On the datasheet, in case of 3.3V/2.5V clock source, it recommends to use capacitance for voltage divider.Is it possible to use resistance for voltage divider?(We assume that it depends on oscilliator drive capavility.)<Question4>We would like to confirm VOSC(Input voltage for 25 MHz Oscillator).If we use following oscillator for XI, VIH and VIL are satisfied with Electrical Characteristics.-VOH =Vcc 90% = 1.62V-VOL=Vcc 10％ =0.18VHowever, voltage will be 1.62V-0.18V=1.44V, so VOSC(1.5V～1.9Vpp) will be out of spec.So, is VOSC 0.9Vpp(typ) like as DP83826? Because XI's VDDIO level is 1.8V, so DP83867's XI voltage level is 1.8V. Is our recognition correct?
Kind regards,Hirotaka Matsumoto
Hi teamIf you have some update, could you share us?Kind regards,Hirotaka Matsumoto
In reply to Hirotaka Matsumoto:
Please find answers in order of the questions here :
1. Yes XI has an internal bias. We can't disclose the exact architecture here.
2. Yes R55 is not required.
3. Resistor divider will either load the driver (as you mentioned) or if the resistor value selected is too high, then it may cause slower rise/fall time. We recommend using caps.
4. Sorry I dont think I understand the question.Can you explain a bit more about why are you subtracting 0.18V and what are you referening to when you are saying that vosc = 0.9V in 826?
Vikram sanThank you for your reply.4. Sorry I dont think I understand the question.Can you explain a bit more about why are you subtracting 0.18V and what are you referening to when you are saying that vosc = 0.9V in 826?->In case of DP83826 with VDDIO=1.8V, OSC common voltage is 0.9V. So, we assume that this voltage is the same as DP83867's VOSC.And then, when we use following 1.8V output oscillator, voltage swing will be 1.62V-0.18V=1.44V.-VOH =Vcc 90% = 1.62V-VOL=Vcc 10％ =0.18VIf VOS minimum is 1.4V, there is no enought electrical tolerance.Therefore, DP83867 XI's VDDIO is level 1.8V, we think that VOSC voltage is 0.9V(typ) the same as DP83826.Is our recognition wrong?Kind regards,Hirotaka Matsumoto
Vikram sanWe guess that your days are so busy, however if you have some update, could you share us?Kind regards,Hirotaka Matsumoto
we have been solving similar problems for a long time with TI support, but without result yet.
Some XI clock configurations and measurements can be found here:
and thread continuation here:
and other people seems to be solving this problem too:
I am waiting for some confirmation from design team regarding interpretation of VOSC.
Vikram sanOK, we are waitting for your update!Kind regards,Hirotaka Matsumoto
Thanks for your patience. I got the confirmation from team that meeting VIH and VIL of XI should be sufficient for PHY. Vosc min value is higher than VIH for extra guard band but is not a necessary spec. To remove confusion Vosc min value will be removed and only Vosc max value will be retained in next datasheet revision.
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