DP83867E: About XIN pin

Vikram san

Thank you so much for your cooperation always!

We have several additional questions.

<Question1>
In case of 3.3V and 2.5V clock source, DC blocking caps require.
So, XI has internal bias voltage, right?
(Is XI Pierce oscillator?)


<Question2>
In relation to <Question1>, if XI is Pierce oscillator, it seems that R55 of DP83867EVM is unnecessary.(Pleas refer to following circuit.)
Because there is bias resistance internally.
Is our recognition correct?



<Question3>
On the datasheet, in case of 3.3V/2.5V clock source, it recommends to use capacitance for voltage divider.
Is it possible to use resistance for voltage divider?(We assume that it depends on oscilliator drive capavility.)

<Question4>
We would like to confirm VOSC(Input voltage for 25 MHz Oscillator).

If we use following oscillator for XI, VIH and VIL are satisfied with Electrical Characteristics.
-VOH =Vcc 90% = 1.62V
-VOL=Vcc 10％　=0.18V
However, voltage will be 1.62V-0.18V=1.44V, so VOSC(1.5V～1.9Vpp) will be out of spec.
So, is VOSC 0.9Vpp(typ) like as DP83826? Because XI's VDDIO level is 1.8V, so DP83867's XI voltage level is 1.8V.  
Is our recognition correct?

Kind regards,

Hirotaka Matsumoto

Hi team

If you have some update, could you share us?

Kind regards,

Hirotaka Matsumoto

Hello Hirotaka-san,

Please find answers in order of the questions here :

1. Yes XI has an internal bias. We can't disclose the exact architecture here.

2. Yes R55 is not required.

3. Resistor divider will either load the driver (as you mentioned) or if the resistor value selected is too high, then it may cause slower rise/fall time. We recommend using caps.

4. Sorry I dont think I understand the question.Can you explain a bit more about why are you subtracting 0.18V and what are you referening to when you are saying that vosc = 0.9V in 826?

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Regards,

Vikram

Vikram san

Thank you for your reply.

4. Sorry I dont think I understand the question.Can you explain a bit more about why are you subtracting 0.18V and what are you referening to when you are saying that vosc = 0.9V in 826?
->In case of DP83826 with VDDIO=1.8V, OSC common voltage is 0.9V. So, we assume that this voltage is the same as DP83867's VOSC.

And then, when we use  following 1.8V output oscillator, voltage swing will be 1.62V-0.18V=1.44V.
-VOH =Vcc 90% = 1.62V
-VOL=Vcc 10％　=0.18V
If VOS minimum is 1.4V, there is no enought electrical tolerance.

Therefore, DP83867 XI's VDDIO is level 1.8V, we think that VOSC voltage is 0.9V(typ) the same as DP83826.
Is our recognition wrong?

Kind regards,

Hirotaka Matsumoto

Vikram san

We guess that your days are so busy, however if you have some update, could you share us?

Kind regards,

Hirotaka Matsumoto

Hello Ishiwata,

we have been solving similar problems for a long time with TI support, but without result yet.

Some XI clock configurations and measurements can be found here:

e2e.ti.com/.../911513

and thread continuation here:

e2e.ti.com/.../949393

and other people seems to be solving this problem too:

e2e.ti.com/.../974168

Hello Hirotaka-san,

I am waiting for some confirmation from design team regarding interpretation of VOSC.

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Regards,

Vikram

Vikram san

OK, we are waitting for your update!

Kind regards,

Hirotaka Matsumoto

Hello Hirotaka-san,

Thanks for your patience. I got the confirmation from team that meeting VIH and VIL of XI should be sufficient for PHY. Vosc min value is higher than VIH for extra guard band but is not a necessary spec. To remove confusion Vosc min value will be removed and only Vosc max value will be retained in next datasheet revision.

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Regards,

Vikram

Vikram san

Thank you for your reply.
OK, we got your circumstance.

To remove confusion Vosc min value will be removed and only Vosc max value will be retained in next datasheet revision.
->We would like to confirm one point.
   If oscillator voltage level is 3.3V or 2.5V, it requires Vosc min value will be removed level.(there is no VIH or VIL level for AC-coupling.)
   If Vosc min value is removed, how should we judge good appropriate swing level?
   Or, 3.3V or 2.5V with AC-coupling will be removed also?

Kind regards,

Hirotaka Matsumoto

Vikram san

We guess that your days are so busy, however if you have some update, could you share us?

Kind regards,

Hirotaka Matsumoto

Hello Hirotaka-san,

I understand your concern. Do you think keeping Vosc min as VIH will be more apt for understanding the requirements correctly?

For 867, we will have to continue using cap divider for 3.3V and 2.5V.

--

Regards,

Vikram

Vikram san

Thank you for your reply.

XI uses Pierce oscillator, so there is 1/2 VCC bias.
In case of AC-coupling, the threshold voltage level depends on voltage swing between Vosc min(threshold level) and Vosc max(Maximum input level).
So, in this case,  Vosc min will be threshold voltage.
That's why, we assume that Vosc min is necessary.

Is our recognition correct?

Kind regards,

Hirotaka Matsumoto

Vikram san

If you have some update, could you share us?

Kind regards,

Hirotaka Matsumoto

Vikram san

Thank you so much for your reply.

OK, we would like to confirm the conclusion.

1. In case of AC-Coupling with Oscillator, Vosc min and Vosc max are necessary for spec(swing level).
2. In case of DC-Coupling(direct connection) with Oscillator, VIH and VIL are necessary for spec.
3. In relation to "1.",  if Vosc min is less than 1.4V? or 1.0V?, it might cause packet errors.(Please refer to https://e2e.ti.com/support/interface/f/138/p/805173/2996134)

So, should we consider using two following ways to be filled with spec?  
-External oscillator : 1.8V LVCMOS type
-Crystal

Kind regards,

Hirotaka Matsumoto

Vikram san

If you have some update, could you share us?

Kind regards,

Hirotaka Matsumoto