DS90UB913A-Q1: followup on https://e2e.ti.com/support/interface/f/138/t/654458

bandit gangwere

Part Number: DS90UB913A-Q1
Other Parts Discussed in Thread: TMP102

I carefully read support/interface/f/138/t/654458.

We are using the 913/914 to move video from a remote device to the main box. The cord is about 6 feet. I need to run the BIST at powerup, and monitor the error registers while running. I followed the sequence in the referred forum post. My I2C master is on the DES. I have a TMP102 temperature I2C device on the SER as an example I2C device to check the link.

I am using an FTDI4222 board for the I2C. USB to the host, where my program is running. The read of the remote TMP102 is good, with proper clock stretching.

What I discovered, in no particular order

1. I set the DES reg x12 = x97. My I2C channel went dead. I could not read my little I2C device on the SER. Changing x12 = x17 fixed that

2. I set SER reg x2D to x0F; set DES reg x42 = x02; start/stop BIST (DES reg x24 = x03; wait 1000 uSec; x24 = x00). The DES reg x25 == 0!!!

3. same thing, but DES reg x42 = x01. DES reg x25 == x0F

4. My problem with this sequence is the BIST does not actually force any errors. All it shows is DES reg x25 is not changed during the BIST. Zero errors are actually injected.

5. Is there a way to actually inject any kind of errors into the video stream? If I am reading the datasheet right. the SER can/does generate a test video if nothing else is going on (not getting a PCLK from the video source, IIRC)

6. I do have a note one can mess with the EQ register values. I am going to try that.

Yours .. bandit

========================= sequence ======================================

#define SER_7ADDR 0x58

#define SER_8ADDR 0xB0

#define DES_7ADDR 0x60

#define DES_8ADDR 0xC0

#define TMP102_7ADDR 0x48

#define TMP102_8ADDR 0x90

I2C_TBL setup_back_channel_tbl[] =

{

//==============================================================

// setup the I2C backchannel

// { TBL_ACT_STR, 0, "enable back channel" },

// reg x01 = x06: enable back channel; reset logic

// reg x01 = x05: enable back channel; reset logic + regs

//==============================================================

// len slave data

{ TBL_ACT_WRITE, 2, DES_7ADDR, 0x01, 0x05 }, // enable bk ch

{ TBL_ACT_DELAY, 100 }, // delay 100 millisec

{ TBL_ACT_WRITE, 2, DES_7ADDR, 0x03, 0xE9 }, // I2C passthru

{ TBL_ACT_WRITE, 2, DES_7ADDR, 0x21, 0x17 }, // I2C passthru

//==============================================================

// the TMP102 remap

// { TBL_ACT_STR, 0, "remap TMP102" },

//==============================================================

{ TBL_ACT_WRITE, 2, DES_7ADDR, 0x08, TMP102_8ADDR }, // Slave ID[1]

{ TBL_ACT_WRITE, 2, DES_7ADDR, 0x10, TMP102_8ADDR }, // Slave Alias[1]

//==============================================================

// read the DES DEV ID

// { TBL_ACT_STR, 0, "read 914 DES DEV_ID s/b SER_8ADDR" },

//==============================================================

{ TBL_ACT_WRITE, 1, DES_7ADDR, 0x06 }, // write reg x06

{ TBL_ACT_READ, 1, DES_7ADDR, /* rd buf */ }, // read the register

//==============================================================

// read the DES initial err count

//==============================================================

{ TBL_ACT_WRITE, 1, DES_7ADDR, 0x25 }, // BIST err count reg

{ TBL_ACT_READ, 1, DES_7ADDR, /* rd buf */ }, // read the count

//==============================================================

// According to the 914 datasheet:

// set 913 reg x2D [6:0] = the desired BIST err count

// set 914 reg x24 = 0x03 to put the 914 in BIST mode

// set 914 reg x24 = 0x08 to put the 914 in regular mode

// read 914 reg x25 for the BIST err count

//==============================================================

// According to BIST force error 913_914.txt

// this is the SER init

//==============================================================

// x03 = xE5 resets the CRC error count

// x03 = 80 = RX CRC Checker Enable

// 40 = TX Parity Generator Enable

// 20 = CRC Error Reset

// 04 = I2C passthrough

// 01 = TRFB = parallel interface strobed on rising edge

// --

// E5 = first to reset the CRC error count

// C5 = ready to run (x20 bit NOT auto reset)

//==============================================================

#if 1

{ TBL_ACT_WRITE, 2, SER_7ADDR, 0x03, 0xE5 },

{ TBL_ACT_WRITE, 2, SER_7ADDR, 0x03, 0xC5 },

{ TBL_ACT_DELAY, 10 }, // delay 10 millisec - needed?

#endif

//==============================================================

// read the temp sensor to makke sure everything setup

//==============================================================

#define DO_BIST 1

#if DO_BIST

//==============================================================

// write the err count

// this works:

// { TBL_ACT_WRITE, 2, SER_7ADDR, 0x2D, 0x0F }, // set exp err count

// set BIST mode ON

// Delay (not sure really needed)

// set BIST mode OFF

// 914 reg x25 == x0F

// The 913 datasheet says hitting the (self-clearing) bit x80

// will incr the count. Wht it really does is set [6:0]

// to 0 (because 0x80 [6:0] == 0)

// The real result id the '914 x25 == 0

// { TBL_ACT_WRITE, 2, SER_7ADDR, 0x2D, 0x80 }, // inject err

// BIST force error 913_914.txt insits on a sleep(1)

// not sure why && sleep(1) is in sec or milliSec

//==============================================================

{ TBL_ACT_WRITE, 2, SER_7ADDR, 0x2D, 0x0F }, // set expected err count

{ TBL_ACT_DELAY, 10 }, // delay 10 millisec

//==============================================================

// supposed to inject CRC errors

//==============================================================

{ TBL_ACT_WRITE, 2, DES_7ADDR, 0x42, 0x01 }, // force CRC

//==============================================================

// start BIST - we are going thru the DES

// { TBL_ACT_STR, 0, "start BIST" },

// wait 100 mSec

// stop BIST

//==============================================================

{ TBL_ACT_WRITE, 2, DES_7ADDR, 0x24, 0x03 }, // start BIST

{ TBL_ACT_DELAY, 1000 }, // delay 1000 millisec

{ TBL_ACT_WRITE, 2, DES_7ADDR, 0x24, 0x00 }, // stop BIST

{ TBL_ACT_DELAY, 100 }, // delay 100 millisec

//==============================================================

// look at the error counts

// { TBL_ACT_STR, 0, "BIST err count before read 0" },

//==============================================================

// { TBL_ACT_MARK },

{ TBL_ACT_WRITE, 1, DES_7ADDR, 0x25 }, // BIST err count reg

{ TBL_ACT_READ, 1, DES_7ADDR, /* rd buf */ }, // read the count

// { TBL_ACT_GOTO },

#endif // DO_BIST

//======================================================

// read the sensor to make sure I2C path works

//======================================================

#if 1 // read temp sensor

//======================================================

// loop, reading the temp sensor

// BIST mode OFF

// read the TMP102 slave at the end of the I2C cghain

// (loop until ctl-C)

//======================================================

{ TBL_ACT_MARK },

{ TBL_ACT_READ, 2, 0x48, /* rd buf */ }, // read TMP102

{ TBL_ACT_DELAY, 100 }, // delay 100 millisec

{ TBL_ACT_GOTO }, // loop to TBL_ACT_MARK

#endif // read temp sensor

//======================================================

// table end

//======================================================

{ TBL_ACT_END, 0, {} }

};

================================= results =============================

== init DES

writing 2: 01 05

I2C master write data to the slave(0X60)...

writing 2: 03 E9

I2C master write data to the slave(0X60)...

writing 2: 21 17

I2C master write data to the slave(0X60)...

writing 2: 08 90

I2C master write data to the slave(0X60)...

writing 2: 10 90

I2C master write data to the slave(0X60)...

writing 1: 06

I2C master write data to the slave(0X60)...

I2C master read 1 bytes data from the slave(0X60)...

exp(1) just read 1 bytes: B0

=== read the error count

writing 1: 25

I2C master write data to the slave(0X60)...

I2C master read 1 bytes data from the slave(0X60)...

exp(1) just read 1 bytes: 00

=== SER init

writing 2: 03 E5

I2C master write data to the slave(0X58)...

writing 2: 03 C5

I2C master write data to the slave(0X58)...

=== BIST: setting error count to <> 0

writing 2: 2D 0F

I2C master write data to the slave(0X58)...

=== supposed to inject an error

writing 2: 42 01

I2C master write data to the slave(0X60)...

=== Start/Stop BIST (1000 uSec delay)

writing 2: 24 03

I2C master write data to the slave(0X60)...

writing 2: 24 00

I2C master write data to the slave(0X60)...

=== Read error count

writing 1: 25

I2C master write data to the slave(0X60)...

I2C master read 1 bytes data from the slave(0X60)...

exp(1) just read 1 bytes: 0F

=== read TMP102 to make sure I2C works

I2C master read 2 bytes data from the slave(0X48)...

exp(2) just read 2 bytes: 18 70

I2C master read 2 bytes data from the slave(0X48)...

exp(2) just read 2 bytes: 18 80

over 5 years ago

0 Charley Cai over 5 years ago

TI__Genius 12866 points

Hi,
In step 3
3. same thing, but DES reg x42 = x01. DES reg x25 == x0F

The DES does record the correct amount of error. DES reg x25 == x0F matches the SER setting reg x2D to x0F.

You could force errors during normal operation mode by configuring SER reg 0x2D[7] (forward channel error), and DES reg 0x42 (back channel error).

Forward channel error status shall be read from DES register 0x1A and 0x1B.
Back channel error shall be read from SER register 0xA and 0x0B

0 bandit gangwere over 5 years ago in reply to Charley Cai

Intellectual 855 points

This is my sequence.

Before BIST

[DES BIST error count ] read reg x25: [write slave(x60): x25 ] [read slave(0X60)] exp(1) got(1) bytes: x00

[SER CRC error count ] read reg x2A: [write slave(x58): x2A ] [read slave(0X58)] exp(1) got(1) bytes: x00

BIST sequence

====== START BIST SEQUENCE ======
[set exp err count ] [write slave(x58): x2D x0F ]
[force CRC ] [write slave(x60): x42 x01 ]
[start BIST ] [write slave(x60): x24 x03 ]
[stop BIST ] [write slave(x60): x24 x00 ]

After BIST

[DES BIST err count reg ] read reg x25: [write slave(x60): x25 ] [read slave(0X60)] exp(1) got(1) bytes: x0F
[SER BIST err count reg ] read reg x2A: [write slave(x58): x2A ] [read slave(0X58)] exp(1) got(1) bytes: x00

SO - looks like things are actually working correctly.

Questions:

1) I need to clarify the Nomenclature: "Forward Channel" means the video link, "Back channel" means the I2C ???

2) Quote: You could force errors during normal operation mode by configuring SER reg 0x2D[7] (forward channel error), and DES reg 0x42 (back channel error).

On the DES, register pair x18/x19 (LS/MS parity error threshold) are == 0. This implies that any parity errors on the Forward channel will NOT be counted in DES register pair x1A/x1B. Is that true? Why?

3) In the "BIST Force error.txt" sequence, the command "time.sleep(1)" obviously is a delay BUT - what time scale is the argument? milliSec? Seconds? Fortnights?

Please advise....

BTW, I HIGHLY recommend getting the FTDI FT4222 eval board for the I2C master. Digikey for about $15. (Not associated with FTDI in any manner) Has clock stretching. I wrote the app that generated my slime trail. Dirt simple to use. (Well, getting the drivers installed can be a bit tricky, but that is Window's fault.)

Thanks! ... bandit

(attached: full slime trail...)

better_BIST_sequence.txt

  Flags= 0x2, (DEVICE_CLOSED, High-speed USB)
  Type= 0xa
  ID= 0x403601c
  LocId= 0x0
  SerialNumber= A
  Description= FT4222 A
  ftHandle= 0x0


Init FT4222 as I2C master
====== setup the DES ======
[enable bk ch                  ] [write slave(x60): x01 x05 ]
[I2C passthru                  ] [write slave(x60): x03 xE9 ]
[I2C ctl 1                     ] [write slave(x60): x21 x17 ]
====== remap TMP102 ======
[Slave ID[0]                   ] [write slave(x60): x08 x90 ]
[Slave Alias[0]                ] [write slave(x60): x10 x90 ]
====== remap SER ======
[set SER_ID                    ] [write slave(x60): x06 xB0 ]
[set SER_Alias                 ] [write slave(x60): x07 xB0 ]
[read DES_ID (exp(xB0)         ] read reg x06: [write slave(x60): x06 ] [read slave(0X60)] exp(1) got(1) bytes: xB0
[read DES_Alias (exp(xB0)      ] read reg x07: [write slave(x60): x07 ] [read slave(0X60)] exp(1) got(1) bytes: xB0
====== DES: general read registers ======
[DES RESET                     ] read reg x01: [write slave(x60): x01 ] [read slave(0X60)] exp(1) got(1) bytes: x04
[DES general config 0          ] read reg x02: [write slave(x60): x02 ] [read slave(0X60)] exp(1) got(1) bytes: x00
[DES general config 1          ] read reg x03: [write slave(x60): x03 ] [read slave(0X60)] exp(1) got(1) bytes: xE9
[DES EQ control                ] read reg x04: [write slave(x60): x04 ] [read slave(0X60)] exp(1) got(1) bytes: x00
[DES SER_ID                    ] read reg x06: [write slave(x60): x06 ] [read slave(0X60)] exp(1) got(1) bytes: xB0
[DES SER_ALIAS                 ] read reg x07: [write slave(x60): x07 ] [read slave(0X60)] exp(1) got(1) bytes: xB0
[DES LS parity error threshold ] read reg x18: [write slave(x60): x18 ] [read slave(0X60)] exp(1) got(1) bytes: x00
[DES MS parity error threshold ] read reg x19: [write slave(x60): x19 ] [read slave(0X60)] exp(1) got(1) bytes: x01
[DES LS parity error count     ] read reg x1A: [write slave(x60): x1A ] [read slave(0X60)] exp(1) got(1) bytes: x00
[DES MS parity error count     ] read reg x1B: [write slave(x60): x1B ] [read slave(0X60)] exp(1) got(1) bytes: x00
[DES General status            ] read reg x1C: [write slave(x60): x1C ] [read slave(0X60)] exp(1) got(1) bytes: x03
[DES MODE/OSS select           ] read reg x1F: [write slave(x60): x1F ] [read slave(0X60)] exp(1) got(1) bytes: x04
[DES I2C ctl 1                 ] read reg x21: [write slave(x60): x21 ] [read slave(0X60)] exp(1) got(1) bytes: x17
[DES I2C ctl 2                 ] read reg x22: [write slave(x60): x22 ] [read slave(0X60)] exp(1) got(1) bytes: x00
[DES BIST control              ] read reg x24: [write slave(x60): x24 ] [read slave(0X60)] exp(1) got(1) bytes: x08
[DES BIST error count          ] read reg x25: [write slave(x60): x25 ] [read slave(0X60)] exp(1) got(1) bytes: x00
[DES CRC force error           ] read reg x42: [write slave(x60): x42 ] [read slave(0X60)] exp(1) got(1) bytes: x00
[DES SEL channel               ] read reg x4C: [write slave(x60): x4C ] [read slave(0X60)] exp(1) got(1) bytes: x00
[DES AEQ test mode select      ] read reg x4D: [write slave(x60): x4D ] [read slave(0X60)] exp(1) got(1) bytes: x20
[DES EQ value                  ] read reg x4E: [write slave(x60): x4E ] [read slave(0X60)] exp(1) got(1) bytes: x00
====== setup the SER ======
[SER reset; enable BC          ] [write slave(x58): x01 x06 ]
[reset CRC err count           ] [write slave(x58): x03 xE5 ]
[ready to run                  ] [write slave(x58): x03 xC5 ]
====== SER dump registers after setup ======
[SER DEV_ID                    ] read reg x00: [write slave(x58): x00 ] [read slave(0X58)] exp(1) got(1) bytes: xB0
[SER PWR/RST                   ] read reg x01: [write slave(x58): x01 ] [read slave(0X58)] exp(1) got(1) bytes: x04
[SER MODE select               ] read reg x05: [write slave(x58): x05 ] [read slave(0X58)] exp(1) got(1) bytes: x14
[SER LS CRC errors             ] read reg x0A: [write slave(x58): x0A ] [read slave(0X58)] exp(1) got(1) bytes: x00
[SER LS CRC errors             ] read reg x0B: [write slave(x58): x0B ] [read slave(0X58)] exp(1) got(1) bytes: x00
[SER general status            ] read reg x0C: [write slave(x58): x0C ] [read slave(0X58)] exp(1) got(1) bytes: x15
[SER general purpose ctl       ] read reg x13: [write slave(x58): x13 ] [read slave(0X58)] exp(1) got(1) bytes: x00
[SER BIST clock src            ] read reg x14: [write slave(x58): x14 ] [read slave(0X58)] exp(1) got(1) bytes: x00
[SER BIST BCC watchdog         ] read reg x1E: [write slave(x58): x1E ] [read slave(0X58)] exp(1) got(1) bytes: xFE
[SER BIST err count reg        ] read reg x25: [write slave(x58): x25 ] [read slave(0X58)] exp(1) got(1) bytes: x00
[SER CRC error count           ] read reg x2A: [write slave(x58): x2A ] [read slave(0X58)] exp(1) got(1) bytes: x00
[SER inject fwd chan err       ] read reg x2D: [write slave(x58): x2D ] [read slave(0X58)] exp(1) got(1) bytes: x0F
====== START BIST SEQUENCE ======
[set exp err count             ] [write slave(x58): x2D x0F ]
[force CRC                     ] [write slave(x60): x42 x01 ]
[start BIST                    ] [write slave(x60): x24 x03 ]
[stop BIST                     ] [write slave(x60): x24 x00 ]
[DES BIST err count reg        ] read reg x25: [write slave(x60): x25 ] [read slave(0X60)] exp(1) got(1) bytes: x0F
[SER BIST err count reg        ] read reg x2A: [write slave(x58): x2A ] [read slave(0X58)] exp(1) got(1) bytes: x00
====== END BIST SEQUENCE ======
[read TMP102                   ] [read slave(0X48)] exp(2) got(2) bytes: x15 xB0
[read TMP102                   ] [read slave(0X48)] exp(2) got(2) bytes: x15 xB0
[read TMP102                   ] [read slave(0X48)] exp(2) got(2) bytes: x15 xB0
[read TMP102                   ] [read slave(0X48)] exp(2) got(2) bytes: x15 xB0
[read TMP102                   ] [read slave(0X48)] exp(2) got(2) bytes: x15 xB0
[read TMP102                   ] [read slave(0X48)] exp(2) got(2) bytes: x15 xB0
[read TMP102                   ] [read slave(0X48)] exp(2) got(2) bytes: x15 xB0

0 Charley Cai over 5 years ago in reply to bandit gangwere

TI__Genius 12866 points

1. Forward channel means data link sent from SER to DES which could contain video data, I2C data, or other control data. Back channel means data link sent from DES to SER which contains I2C data, or control data.

2. 0x19 default should be ==1. If 0x18 and 0x19 both are 0, you are correct that parity error on forward channel will not be counted. Please increase the threshold if you need to count errors.

3. Is "BIST Force error.txt" document from TI. We typically use 1 second delay.

Best Regards,
Charley Cai

0 bandit gangwere over 5 years ago in reply to Charley Cai

Intellectual 855 points

3) In the "BIST Force error.txt" sequence, the command "time.sleep(1)" obviously is a delay

so you are saying the sleep() argument is in seconds?? if so - wow - it tales a second to reset the chip + registers?

0 Charley Cai over 5 years ago in reply to bandit gangwere

TI__Genius 12866 points

Can you attached the "BIST Force error.txt" file?

Best Regards,
Charley Cai

0 bandit gangwere over 5 years ago in reply to Charley Cai

Intellectual 855 points

here you go...

6011.BIST force error 913_914.txt

import time
import sys

DesAddr=0xC0 #default value
SerAddr=0xB0 #default value
board.devAddr = DesAddr
board.WriteReg(0x01,0x06)
board.WriteReg(0x21,0x97)
time.sleep(1)
board.devAddr = SerAddr
--- this resets the digital logic
board.WriteReg(0x03,0xE5) 
board.WriteReg(0x03,0xC5)
board.WriteReg(0x2D,0x0F) #force 0x0f parity error
time.sleep(1)
board.devAddr = DesAddr
board.WriteReg(0x24,0x03) #enable BIST select 50MHz internal clock
time.sleep(10)
board.WriteReg(0x24,0x00) # disable BIST
time.sleep(1)
BIST_ERROR=board.ReadReg(0x25) #read bist errors
print hex(BIST_ERROR)

0 Charley Cai over 5 years ago in reply to bandit gangwere

TI__Genius 12866 points

Yes, the scale is in second.
There's no correlation between this delay and time it takes to reset chip + access registers.

You could reduce the time.sleep(1) delay if needed.

The time.sleep(10) delay is used to control BIST run time. In this case, BIST runs for 10 second.

Best Regards,

Charley Cai

0 bandit gangwere over 5 years ago in reply to Charley Cai

Intellectual 855 points

How long does a reset take?
It should be well under 100 mSec.

And since the error injection via a register on the SER, the error should "occur" very quickly.
I am waiting 200 mSec and the DES error count shows up in the DES.

Thanks ... bandit

0 Charley Cai over 5 years ago in reply to bandit gangwere

TI__Genius 12866 points

It should take 2ms for 913/914 SERDES to reset and relock.
We do not have any timing spec on when forced error would occur

Best Regards,
Charley Cai

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DS90UB913A-Q1: followup on https://e2e.ti.com/support/interface/f/138/t/654458