Please confirm:
1. The voltage limit on all pins is 4V, does this mean the ESD structure does not clamp the pin to the VDDA or VDDIO rail with a diode-like structure?
2. If so, does this mean that if VDDIO or VDDA are at ground, no significant leakage current will flow into the other I/O pins?
3. The XI clock can be 1.8V level regardless of the VDDIO level (1.8V, 2.5V, 3.3V)