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TUSB1210 Timing issue with Zynq-7000, solved or not?

user3997834
Prodigy 10 points
Other Parts Discussed in Thread: TUSB1210

Hi everyone,

I was doing a copy-design based on Zedboard, and I noticed that TUSB1210 has some incompatible issue with Zyng-7000, as the Zedboard Errata said. The main problem is that TUSB1210 MIN output delay (Tdc, Tdd) can be as fast as 0.1ns, and the Zynq-7000 AP SoC need at least 1ns.

But that was 4 years ago. And I checked the most updated TUSB1210 datasheet, REVISED JUNE 2015, the minmum output delay (Tdc, Tdd) was clearly specified as 1.2ns, Table 5-4, Page 18.

So, does this means that the incompatible problem is solved?

I didn't see any post regarding this updating on TI or Xilinx website. If anyone have any reliable information, it would be a great help if you could share with us. Thanks!

Young.