Other Parts Discussed in Thread: STRIKE, ISO1042, ISOW1044, ISO1044
Hi Teams,
Is there a risk of damage when the chip(ISO1050) is subjected to pulse voltage?The following is a description of this voltage:
a.The yellow waveform represents CANH to ground, while the blue waveform represents CANL to ground
b.The maximum peak voltage can reach 87V, lasting for about 20 nanoseconds
c.Description of lightning protection testing conditions:
Strike a common mode 3KA lightning current between CAN+ and PGND,Most of the lightning current of this 3KA is discharged from the CAN+ to PGND through a triode discharge tube,This current is decoupled by a common mode inductor, and then a residual voltage is formed at both ends of the TVS. The pulse voltage waveform of the chip pin to ground measured by the oscilloscope is as follows.
d.The voltage limit given in the ISO1050 device specification is -27V to+40V, which should be the result of DC voltage testing. Is there a risk of damage when the chip is subjected to nanosecond voltage exceeding the specified stress?