How to ensure "reset" of TPS40170-EP after over-current event?

Let me look into it and will respond to your question.

Elderbee,

Can you provide your schematic in Pdf format.

Client schematic page - how can I send this with some degree of privacy (e.g. not post for on a public forum)?

Bump:

How do I send this so that it's not on a public forum (client confidential information)??

Hi Elderbee,

   I am sending you a seperate email to you, so you can share your documents with me. 

Ramesh

Hi Ramesh - not sure if my emails are getting through to you?

Hi  User 4544767

  Yes I have received your schematic as well as scope shots,  Will go thru and provide you feedback on it.

Hi Ramesh - I have finally been able to look at this again (had to measure loop bandwidths of some other supplies).

Instead of changing the UVLO threshold, I added a 100nF capacitor to ground at the UVLO pin on the device, preventing the brownout when the SCR is triggered.

I have to send the circuit to production soon: do you see any problems with such a large UVLO capacitor (perhaps an unintended hysteresis or other instability with the TPS40170 turn-on control loop)?

best regards,

Here is the scope screenshot and circuit with the 100nF added to the UVLO: when the SCR triggers (when '5V' line exceeds 5.25V, t=0s), the UVLO is kept >940mV and the TPS40170 goes through it's normal restart period (ca. 200ms), as expected.

Hi USER4544767,

I did not see any circuit attached tot he e2e post. Did you send it as a separate email to me?

Hi - thank you.

I tried "insert/edit media", but .png files don't appear to get saved to the message (after "post" they dissappear).

After some testing I think Ive been able to add them by to the message with "insert file" instead, so it should be visible in my post now, thank you.

Hi USER4544767,

There is a potential risk with 0.1uF capacitor on UVLO pin.
If Vin drops below 5V quickly during SCR, UVLO might still be above UVLO off threshold. At this condition, because Vin is lower than Vout, the controller will switch with maximum duty cycle. Then if Vin goes back to 12V quickly, due to the delay of control loop, the Vout will be much higher than 5V and damage the load because PWM duty cycle does not decrease in time.
Thus it is not recommended to use 0.1uF capacitor on UVLO pin.

Hi Ramesh - thank you.

I see that this would be a source-load interaction that is hard to predict (depends on how quickly and how the source reacts to an over-current). However, due the presence of the SCR, this would prevent the 5V output from rising above ca. 5.5V, so I think the circuit remains safe.

I will nevertheless try reducing the UVLO capacitor to a lower value and see if the protection function remains active.